ZL9101EVAL1Z Intersil, ZL9101EVAL1Z Datasheet
ZL9101EVAL1Z
Specifications of ZL9101EVAL1Z
Related parts for ZL9101EVAL1Z
ZL9101EVAL1Z Summary of contents
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... The ZL9101EVAL1Z is a 6-layer board that provides a single-phase power rail up to 12A loads. The board is designed to efficiently transfer heat away from the module with passive cooling. A USB to SMBus adapter is used to connect the ZL9101EVAL1Z board to a PC. The PMBus command set is accessed by using the PowerNavigator™ evaluation software. P4 ...
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... Install the PowerNavigator software using the CD included in the ZL9101EVAL1Z kit. For PMBus operation, connect the USB-to- SMBus dongle board the ZL9101EVAL1Z board. Connect the desired load and an appropriate power supply to the input. Place the ENABLE switch in “DISABLE” and turn on the power. ...
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Switching Frequency and PLL The ZL9101M incorporates an internal phase-locked loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin via J7 or J14. When using the internal ...
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... Ref Value Vout 21.5K 1. 31.6K 1. 61.9K 1.80 V R10 110K 2.50 V XX1 R11 147K 3. R10 R11 SG FIGURE 2. ZL9101EVAL1Z CIRCUIT SCHEMATIC C10 C11 C12 680uF 680uF 680uF 6.3V 6.3V 6.3V VOUT VOUT 47uF 47uF 47uF 47uF 6.3V 6.3V 6.3V 6.3V FB+ FB- XX2 ...
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... VIN VOUT VOUT R21 G-ADJ Q2 1 392 392 FDG6301N C31 10uF 25V HW_EN PG R28 187 FIGURE 3. ZL9101EVAL1Z INTERFACE SCHEMATIC VOUT P1 + FB+ VOUT FB- - C19 C20 C21 C22 C23 100uF 100uF 100uF 100uF 100uF 6.3V 6.3V 6.3V 6.3V 6.3V VDD P2 VDD + VDD 3 VDD ...
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... Default Configuration File The following text is loaded into the ZL9101M devices on the ZL9101EVAL1Z evaluation board as the default settings. This configuration file can be loaded using the PowerNavigator™ software, ConfigCheck™ software user-created application. The # symbol denotes a comment line. # Intersil ZL9101M 12/20/2010 ...
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IOUT_UC_FAULT_LIMIT IOUT_AVG_UC_FAULT_LIMIT MFR_IOUT_OC_FAULT_RESPONSE MFR_IOUT_UC_FAULT_RESPONSE MFR_VMON_OV_FAULT_LIMIT VMON_OV_FAULT_RESPONSE MFR_VMON_UV_FAULT_LIMIT VMON_UV_FAULT_RESPONSE VIN_OV_WARN_LIMIT VIN_OV_FAULT_LIMIT VIN_OV_FAULT_RESPONSE VIN_UV_WARN_LIMIT VIN_UV_FAULT_LIMIT VIN_UV_FAULT_RESPONSE OT_WARN_LIMIT OT_FAULT_LIMIT OT_FAULT_RESPONSE UT_WARN_LIMIT UT_FAULT_LIMIT UT_FAULT_RESPONSE PID_TAPS DEADTIME DEADTIME_CONFIG DEADTIME_MAX MAX_DUTY #TRACK_CONFIG #XTEMP_SCALE #XTEMP_OFFSET MFR_CONFIG NLR_CONFIG USER_CONFIG TEMPCO_CONFIG MISC_CONFIG ISHARE_CONFIG INTERLEAVE SEQUENCE DDC_GROUP DDC_CONFIG INDUCTOR STORE_DEFAULT_ALL ...
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Application Note 1625 FIGURE 4. TOP LAYER FIGURE 5. INNER_1 8 AN1625.0 February 4, 2011 ...
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Application Note 1625 FIGURE 6. INNER_2 FIGURE 7. INNER_3 9 AN1625.0 February 4, 2011 ...
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Application Note 1625 FIGURE 8. INNER_4 FIGURE 9. BOTTOM 10 AN1625.0 February 4, 2011 ...
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... FIGURE 10. PHOTO SHOWING JUMPERS AND CONNECTORS Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com ...