ISL6420BEVAL1Z Intersil, ISL6420BEVAL1Z Datasheet - Page 6

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ISL6420BEVAL1Z

Manufacturer Part Number
ISL6420BEVAL1Z
Description
EVAL BOARD 1 FOR ISL6420B
Manufacturer
Intersil
Datasheets

Specifications of ISL6420BEVAL1Z

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Layout Guidelines
DC to DC converter layout is extremely important to
obtain the desired attenuation to the EMI frequencies.
Poor layout practice can cause conducted emissions to
actually couple around the filter components directly into
the input conductors or cause radiated emissions. The
copper traces of power input and output and high current
paths must be sized according to the RMS current
passing through them. Keep the high current loops small
and the path defined. Use single point grounding.
Capacitor lead length must be minimized as much as
possible to reduce ESL. This includes the traces on the PC
board leading up to the capacitor pads. Based on the
layout, voltage transients may reduce the level of the
acceptable max V
case, one can consider the use of snubbers or reduce the
max VIN. Use of a GND plane in a multilayered board is
preferred.
IN
when operating close to 28V. In this
6
Application Note 1504
References
For Intersil documents available on the web, see
http://www.intersil.com/
[1] ISL6420A Data Sheet, Advanced Single
[2] ISL6420B Data Sheet, Advanced Single
Synchronous Buck Pulse-Width Modulation (PWM)
Controller, Intersil Corporation, File No. FN9169.
Synchronous Buck Pulse-Width Modulation (PWM)
Controller, File No. FN6901
November 23, 2009
AN1504.0

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