ISL6420BEVAL2Z Intersil, ISL6420BEVAL2Z Datasheet - Page 12

• Manufacturer Part Number: ISL6420BEVAL2Z
• Description: EVAL BOARD 2 FOR ISL6420B
• Manufacturer: Intersil

Specifications of ISL6420BEVAL2Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CDEL
The PGOOD signal can be delayed by a time
proportional to a CDEL current of 2µA and the value of
the capacitor connected between this pin and ground.
A 0.1µF will typically provide 125ms delay. When in the
Voltage Margining mode, the CDEL current is 100µA
typical and provides the delay for the output voltage
slew rate, 2.5ms typical for the 0.1µF capacitor.
PGND
This pin provides the power ground for the IC. Tie this
pin to the ground plane through the lowest impedance
connection.
PVCC
This pin is the power connection for the gate drivers.
Connect this pin to the VCC5 pin.
VCC5
This pin is the output of the internal 5V LDO. Connect a
minimum of 4.7µF ceramic decoupling capacitor as
close to the IC as possible at this pin. Refer to Table 1.
ENSS
This pin provides enable/disable function and soft-start
for the PWM output. The output drivers are turned off
when this pin is held below 1V.
OCSET
Connect a resistor (R
pin to the drain of the upper MOSFET. R
internal 100µA current source (I
MOSFET on resistance r
overcurrent (OC) trip point.
NOTES:
13. The GPIO1/REFIN and GPIO2 pins cannot be left floating.
14. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.
Enable Voltage Margining
No Voltage Margining. Normal
operation with internal reference.
Buffered V
No Voltage Margining. External
reference. Buffered
V
REFOUT
FUNCTION/MODES
= V
REFOUT
REFIN
TABLE 2. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION
= 0.6V.
OCSET
DS(ON)
12
) and a capacitor from this
set the converter
OCSET
Pin Connected to
GND with resistor. It
is used as VMSET.
VMSET/MODE
), and the upper
OCSET
H
H
, an
ISL6420B
Connect a 2.2µF
capacitor for bypass of
external reference.
Connect a 2.2µF
capacitor to GND.
Connect a 2.2µF
capacitor to GND.
REFOUT
GPIO1/REFIN
This is a dual function pin. If VMSET/MODE is not
connected to VCC5 then this pin serves as GPIO1.
Refer to Table 3 for GPIO commands interpretation.
To use GPIO1/REFIN as input reference, connect
VMSET/MODE to VCC5 and GPIO2 to SGND. Connect
the desired reference voltage to the GPIO1/REFIN pin
in the range of 0.6V to 1.25V.
Connect GPIO1/REFIN and VMSET/MODE pins to
VCC5, GPIO2 to SGND, the IC operates with the
internal reference and no voltage margining function.
REFOUT
It provides buffered reference output for REFIN.
Connect 2.2µF decoupling capacitor to this pin.
VMSET/MODE
This pin is a dual function pin. Tie this pin to VCC5 to
disable voltage margining. When not tied to VCC5, this
pin serves as VMSET. Connect a resistor from this pin
to ground to set delta for voltage margining.
If voltage margining and external reference tracking
mode are not needed, VNSET/MODE, GPIO1/REFIN
and GPIO2 all together can be tied directly to ground.
GPIO2
This is general purpose IO pin for voltage margining.
Refer to Table 3.
Exposed Thermal Pad
This pad is electrically isolated. Connect this pad to
the signal ground plane using at least five vias for a
robust thermal conduction path.
PIN CONFIGURATIONS
Serves as a general
purpose I/O. Refer to
Table 3.
Connect to an
external reference
voltage source
(0.6V to 1.25V)
GPIO1/REFIN
H (Note 14)
Serves as a general
purpose I/O. Refer to
Table 3.
GPIO2
December 4, 2009
L
L
FN6901.1