ADC16DV160HFEB/NOPB National Semiconductor, ADC16DV160HFEB/NOPB Datasheet - Page 16

• Manufacturer Part Number: ADC16DV160HFEB/NOPB
• Description: EVAL BOARD FOR ADC16DV160
• Manufacturer: National Semiconductor

Specifications of ADC16DV160HFEB/NOPB

• Number Of Adc's: *
• Number Of Bits: 16
• Sampling Rate (per Second): 160M
• Data Interface: *
• Inputs Per Adc: *
• Input Range: *
• Voltage Supply Source: Analog and Digital
• Utilized Ic / Part: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Functional Description
Operating on dual +1.8V and +3.0V supplies, the AD-
C16DV160 digitizes a differential analog input signal to 16
bits, using a differential pipelined architecture with error cor-
rection circuitry and an on-chip sample-and-hold circuit to
ensure maximum performance. The user has the choice of
using an internal 1.2V stable reference, or using an external
1.2V reference. The internal 1.2V reference has a high output
impedance of > 9 kΩ and can be easily over-driven by an
external reference. A 3-wire SPI-compatible serial interface
facilitates programming and control of the ADC16DV160.
ADC Architecture
The ADC16DV160 architecture consists of a dual channel
highly linear and wide bandwidth sample-and-hold circuit, fol-
lowed by a switched capacitor pipeline ADC. Each stage of
the pipeline ADC consists of low resolution flash sub-ADC
and an inter-stage multiplying digital-to-analog converter
(MDAC), which is a switched capacitor amplifier with a fixed
stage signal gain and DC level shifting circuits. The amount
of DC level shifting is dependent on sub-ADC digital output
code. A 16-bit final digital output is the result of the digital error
correction logic, which receives the digital output of each
stage including redundant bits to correct offset error of each
sub-ADC.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC16DV160:
2.7V
1.7V
1.7V
20 MSPS
V
V
REF
CM
= 1.15V (from V
≤
≤
≤
≤
V
V
V
1.2V
A3.0
A1.8
DR
≤
≤
F
≤
≤
CLK
1.9V
3.6V
1.9V
≤
160 MSPS
RM
)
FIGURE 4. Simplified Switched-Capacitor Sample-and-hold Circuit
16
2.0 ANALOG INPUTS
The analog input circuit of the ADC16DV160 is a differential
switched capacitor sample-and-hold circuit (see
provides optimum dynamic performance wide input frequency
range with minimum power consumption. The clock signal al-
ternates sample mode (Q
ed low jitter duty cycle stabilizer ensures constant optimal
sample and hold time over a wide range of input clock duty
cycle. The duty cycle stabilizer is always turned on during
normal operation.
During sample mode, analog signals (V
across two sampling capacitors (C
sample-and-hold circuit is idle. The dynamic performance of
the ADC16DV160 is likely determined during sampling mode.
The sampled analog inputs (V
mode by connecting input side of the sampling capacitors to
output of the amplifier in the sample-and-hold circuit while
driving pipeline ADC core.
The signal source, which drives the ADC16DV160, is recom-
mended to have a source impedance less than 100Ω over a
wide frequency range for optimal dynamic performance.
A shunt capacitor can be placed across the inputs to provide
high frequency dynamic charging current during sample
mode and also absorb any switching charge coming from the
ADC16DV160. A shunt capacitor can be placed across each
input to GND for similar purpose. Smaller physical size and
low ESR and ESL shunt capacitors are recommended.
The value of shunt capacitance should be carefully chosen to
optimize the dynamic performance at specific input frequency
range. Larger value shunt capacitors can be used for lower
input frequencies, but the value has to be reduced at high
input frequencies.
Balancing impedance at positive and negative input pin over
entire signal path must be ensured for optimal dynamic per-
formance.
30101406
S
) and hold mode (Q
IN+
, V
S
) while the amplifier in the
IN-
) are held during hold
IN+
, V
IN-
H
) are sampled
). An integrat-
Figure
4) that