KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 27

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INPUT
Equivalent Circuits
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform which can be used
to evaluate any of the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and a
family of ADC daughtercards. This USB based platform
allows a user to quickly evaluate the ADC’s performance at a
user’s specific application frequency requirements. More
information is available at
http://www.intersil.com/converters/adc_eval_platform/
DATA
DATA
2mA OR
2mA OR
AVDD
3mA
3mA
FIGURE 42. TRI-LEVEL DIGITAL INPUTS
OVDD
280O Ω
FIGURE 44. LVDS OUTPUTS
75kO
75kO
Ω
Ω
AVDD
DATA
DATA
(Continued)
27
75kO
Ω
AVDD
OVDD
0.535V
OVDD
75kO
Ω
AVDD
+
–
FIGURE 46. VCM_OUT OUTPUT
D[11:0]P
D[11:0]N
SENSE
KAD5512P-50
LOGIC
TO
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex board
designs benefit from isolating the analog and digital
sections. Analog supply and ground planes should be laid
out under signal and clock inputs. Locate the digital planes
under outputs and logic pins. Grounds should be joined
under the chip.
(20k PULL-UP
INPUT
ON RESETN
ONLY)
DATA
AVDD
OVDD
FIGURE 45. CMOS OUTPUTS
FIGURE 43. DIGITAL INPUTS
280Ω
VCM
OVDD
20kΩ
OVDD
OVDD
OVDD
D[11:0]
LOGIC
TO
October 9, 2009
FN6805.3