ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 8

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital Specifications
Timing Diagrams
CMOS INPUTS
Input Current High
(SDIO, RESETN, CSB, SCLK)
Input Current Low
(SDIO, RESETN, CSB, SCLK)
Input Voltage High
(SDIO, RESETN, CSB, SCLK)
Input Voltage Low
(SDIO, RESETN, CSB, SCLK)
Input Current High
(OUTMODE, NAPSLP,
OUTFMT) (Note 14)
Input Current Low
(OUTMODE, NAPSLP,
OUTFMT)
Input Capacitance
LVDS INPUTS (ClkdivrstP, ClkdivrstN)
Input Common Mode Range
Input Differential Swing
(peak to peak, single ended)
Input Pull-up and Pull-down
Resistance
LVDS OUTPUTS
Differential Output Voltage
(Note 15)
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
CLKOUTN
CLKOUTP
D[11:0]P
D[11:0]N
CLKN
CLKP
INN
INP
PARAMETER
FIGURE 2. LVDS TIMING DIAGRAM
t
CPD
t
A
SAMPLE N
t
PD
t
DC
DATA
N-L
LATENCY= L CYCLES
8
N-L+1
DATA
V
SYMBOL
OS_LVDS
V
R
V
V
V
C
V
I
V
I
I
I
V
ICM
t
t
t
t
Ipu
OH
IH
IH
IL
IL
ID
OL
IH
DI
IL
R
F
R
F
T
N-L+2
DATA
V
V
3mA Mode
3mA Mode
I
I
OH
OL
IN
IN
CONDITIONS
= 1mA
= 1.8V
= 0V
= -500µA
ISLA112P50
DATA
N
OVDD - 0.3
CLKOUTN
CLKOUTP
D[11:0]N
D[11:0]P
MIN
1.17
825
250
950
-25
-40
15
CLKN
CLKP
0
INP
INN
FIGURE 3. CMOS TIMING DIAGRAM
t
CPD
t
A
SAMPLE N
OVDD - 0.1
TYP
620
965
625
625
t
-12
0.1
25
25
PD
1
3
1
2
2
t
DC
DATA
N-L
LATENCY= L CYCLES
N-L+1
DATA
MAX
1575
0.63
450
980
-15
0.3
10
40
-5
N-L+2
DATA
UNITS
June 17, 2010
mV
mV
mV
MΩ
mV
µA
µA
µA
µA
pF
ps
ps
ns
ns
V
V
V
V
P-P
FN7604.1
DATA
N