DK-RV-1.8-TRK-33 austriamicrosystems, DK-RV-1.8-TRK-33 Datasheet - Page 6

• Manufacturer Part Number: DK-RV-1.8-TRK-33
• Description: EVAL KIT SQUIGGLE MOTOR + SENSOR
• Manufacturer: austriamicrosystems
• Series: SQUIGGLE®, TRACKER™r

Specifications of DK-RV-1.8-TRK-33

• Main Purpose: Power Management, Motor Control
• Utilized Ic / Part: SQL-RV-1.8-6-12, NSE-5310, MC-3300-RV, NSD-2101
• Primary Attributes: Linear Motor, Driver and Position Encoder
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Secondary Attributes: -

NSD-2101
Data Sheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
Figure 1
The input voltage is supplied directly to the full bridge driver. With a full bridge drive, each piezo element sees twice the input voltage (2 x VDD).
However, the average input voltage to the piezo can be regulated by the ASIC between VDD and 2 x VDD. This average voltage, which can be
set via I²C along with the duty cycle (or pulse width) of the drive signal, determines the speed of the motor. The result being at lower speeds, the
motor consumes less power.
I²C registers also define the initial switching frequency of the motor, which can be adjusted from 50 kHz to 200 kHz based on the type of motor
being driven. Other registers control motor direction and the number of pulses the motor is active (correlating to distance traveled). The XPD
input enables a stand-by mode.
7.1 Output Drivers
The output drivers operate rail to rail and are capable of driving capacitive load up to 60nF. The concept is based on two full bridges per motor.
The reduced voltage Squiggle motor consists of 2 plates per phase and 2 phases. In power down mode the output drivers are pulled to ground.
The same applies when the motor is off.
Table 6. Characteristics for Output Drivers
1. Measured at 10% to 90% of minimum VDD=2.3V. Maximum with 4 clocks dead-time.
2. Current limit is valid for full bridge and half bridge configuration. Due to the dynamic behavior of the output driver the maximum current
3. For this frequency range, frequency tracking is implemented.
4. Error of dead time is maximum +1 VCO clock cycle.
www.austriamicrosystems.com/NSD-2101
limit can not be reached under all conditions. Device can only be used for direct motor drive.
Symbol
C
Supply input
LDO and bypass capacitors
I²C interface
Registers
Oscillator
Frequency tracking
Full bridge driver
LOAD
f
f
DFR
f
I
t
f
PSE
DC
f
f
lim
DT
PS
tr
tf
shows the main building blocks of the system:
Rise/fall time from 0.23V to 2.07V and
Current limit for driver outputs
Switching frequency duty cycle
Drive frequency range
Dead time (additional)
Load capacitance
Phase shift error
Parameter
Phase shift
vice versa
3
2
VCO clock cycles
Revision 0.4
C
Conditions
VDD=2.3V
LOAD
50nF,
1
4
1000
0.08
-160
Min
10
50
1
2
Typ
4
1600
Max
200
+90
0.8
±3
60
50
9
Units
kHz
deg
deg
mA
µs
nF
%
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