ISL59114IRUZ-EVALZ Intersil, ISL59114IRUZ-EVALZ Datasheet
ISL59114IRUZ-EVALZ
Specifications of ISL59114IRUZ-EVALZ
Related parts for ISL59114IRUZ-EVALZ
ISL59114IRUZ-EVALZ Summary of contents
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... Ordering Information PART NUMBER (Note) PART MARKING ISL59114IRUZ-T7 FJ NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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Absolute Maximum Ratings (T = +25°C) A Supply Voltage from V to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V DD Input Voltage ...
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Electrical Specifications V = 3.3V PARAMETER DESCRIPTION AC PERFORMANCE BW ±0.1dB Bandwidth 0.1dB BW -3dB Bandwidth 3dB Normalized Stopband Gain dG Differential Gain dP Differential Phase D/DT Group Delay Variation SNR Signal to Noise Ratio T Enable Time ...
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Pin Descriptions PIN NUMBER PIN NAME CLAMP CVBS 7 C OUT 8 CVBS OUT 9 Y OUT 10 GND Typical Performance Curves 5 0 ...
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Typical Performance Curves 270 V = +3. 150Ω L 180 90 0 -90 -180 -270 100k 1M FREQUENCY (Hz) FIGURE 5. PHASE vs FREQUENCY FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE ...
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Typical Performance Curves 3.5 3.0 2 +3. 150Ω 2.5V OUT P-P 1 26.4ns RISE 1.0 T 0.5 0.0 -120 - 120 180 240 300 360 420 480 ...
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Typical Performance Curves V = +3. 150Ω L FIGURE 17. GROUP DELAY vs FREQUENCY 100 10kHz 7 ISL59114 (Continued FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE ...
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Typical Performance Curves JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 0.7 0.6 515mW 0.5 0.4 0.3 0.2 0 100 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Application ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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... Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: TERMINAL TIP No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. L MILLIMETERS MIN NOMINAL MAX A 0 ...