EVAL-ADF4360-5EBZ1 Analog Devices Inc, EVAL-ADF4360-5EBZ1 Datasheet - Page 16

• Manufacturer Part Number: EVAL-ADF4360-5EBZ1
• Description: BOARD EVALUATION FOR ADF4360-5
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4360-5EBZ1

• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4360-5
• Primary Attributes: Single Integer-N PLL with VCO
• Secondary Attributes: 1.3GHz, 200kHz PFD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4360-5
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-5 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch.
Table 10. C
C
10 µF
440 nF
N
Value
N
Recommended Interval between Control Latch and N Counter Latch
≥ 5 ms
≥ 600 µs
Capacitance vs. Interval and Phase Noise
POWER-UP
CLOCK
DATA
LE
DD
, DV
DD
LATCH DATA
R COUNTER
, V
VCO
, and CE pins. On
Figure 16. ADF4360-5 Power-Up Timing
LATCH DATA
Rev. A | Page 16 of 24
CONTROL
This interval is necessary to allow the transient behavior of the
ADF4360-5 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the part
and the bias currents of the VCO begins to settle. If these cur-
rents have not settled to within 10% of their steady-state value
and if the N counter latch is then programmed, the VCO may
not be able to oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency band
and the ADF4360-5 may not achieve lock. If the recommended
interval is inserted and the N counter latch is programmed, the
band select logic can choose the correct frequency band and the
part locks to the correct frequency.
The duration of this interval is affected by the value of the ca-
pacitor on the C
the close-in noise of the ADF4360-5 VCO. The recommended
value of this capacitor is 10 µF. Using this value requires an in-
terval of ≥ 5 ms between the latching in of the control latch bits
and latching in of the N counter latch bits. If a shorter delay is
required, this capacitor can be reduced. A slight phase noise
penalty is incurred by this change, which is explained further in
Table 10.
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
REQUIRED INTERVAL
N
pin (Pin 14). This capacitor is used to reduce
Open-Loop Phase Noise @ 10 kHz Offset
−88 dBc
−87 dBc
LATCH DATA
N COUNTER