IP1837TRPBF International Rectifier, IP1837TRPBF Datasheet - Page 25

• Manufacturer Part Number: IP1837TRPBF
• Description: IC DC-DC REG SYNC BUCK LGA
• Manufacturer: International Rectifier
• Series: iPOWIR™r
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of IP1837TRPBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 12 V
• Current - Output: 35A
• Frequency - Switching: 250kHz ~ 1.5MHz
• Voltage - Input: 1.5 V ~ 16 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Package: LGA - 7.7 x 7.7
• Circuit: Single Output
• Iout (a): 35
• Switch Freq (khz): 250 - 1500
• Input Range (v): 1.5 - 16
• Output Range (v): 0.6 - 0.75*Vin
• Internal Bias Ldo: Yes
• Ocp Otp Uvlo Pre-bias Soft Start And: Remote Sense + Body Tracking + Temp Comp OCP
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These result in:
Select crossover frequency F
Since F
the pole and zeros.
Detailed calculation of compensation Type III:
Desired Phase Margin Θ = 80°
Select: C
Calculate: R
Select: R
Calculate: R
Select: R
C
C
F
F
F
F
R
R
R
10
P
P
3
8
Z
Z
3
4
3
2
1
2









F
F
F
2
2
2
2
LC
ESR
s
C
2
0.5
LC
0.5
/2=300kHz
F



F


=25.58kHz
<F
7
o
7
3
8
=4.4MHz
o
*
*
*
= 2.2nF
= 4.22 kΩ
= 7.5 kΩ
*
*
*
*
*
o
F
F
C
1
C
1
1
1
<F
F
3
F
V
10
1
1
1
Z
P
1
F
, C
7
25


7
s
1
o
in
3
, R


*
s
Z
*
*
*
/2<F

sin
sin
*
3
2
*
F
sin
sin
and C
R
8
R
F
300
L
and R

Z
F
3
P
3
2
o
2
m
;
ESR
;


March 3, 2011 | V1.24
4.81
-
*


C
C
;
*
R
, Type III is selected to place
C
4
3
4
kHz

10

R
:
9



o
:
10
1257.31
;
9.62
125.71
;
7.84
kHz
R

R
8
3
o
60
=110 kHz


nF,
7.46
kHz
4.75
, Ω
pF
kHz
Select
,
Select
kΩ
Select
kΩ
,
:
:
C
R
:
Highly Integrated 35A Single‐input Voltage,
10
4
C

3


8.2
57.6
120
nF
Ω
pF
Synchronous Buck Regulator
PROGRAMMING THE CURRENT‐LIMIT
The Current‐Limit threshold can be set by connecting
a resistor (R
The resistor can be selected by using Table 2.
In order to set a trip current of 40A, we may select
R
SETTING THE POWER GOOD THRESHOLD
A window comparator internally sets a lower Power Good
threshold at 0.51V and an upper Power Good threshold at
0.7V. When the voltage at the Voso pin is within the
window set by these thresholds, PGood is asserted.
The power good output PGD is an open drain output.
Hence, it is necessary to use a pull up resistor R
PGD pin to Vcc. The value of the pull‐up resistor must be
chosen such as to limit the current flowing into the PGD
pin, when the output voltage is not in regulation, to less
than 5mA. A typical value used is 10kΩ.
It must be noted that if the voltage on Voso exceeds the
upper threshold 0.7V, not only is PGD de‐asserted, but also
an overvoltage fault is flagged, following which, even if the
overvoltage condition gets resolved, the converter can be
re‐started only by cycling Vcc or Enable.
OCSet
= 54.9K, using Table 2.
OCSet
) from the SW pin to the OCSet pin.
iP1837
PG
from
97600