ISL62882HRTZ-T Intersil, ISL62882HRTZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL62882HRTZ-T
• Description: IC REG PWM 2PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62882HRTZ-T

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
Multiphase R
FIGURE 6. R
Master
Crs2
Clock1
Clock2
Crs1
COMP
PWM1
PWM2
Clock
gmVo
Vcrm
VW
Master
Clock
Vcrs2
Vcrs1
FIGURE 5. R
VW
VW
VW
VW
PRINCIPLES IN STEADY STATE
Vcrm
Vcrs2
3™
COMP
Crm
3™
MODULATOR OPERATION
Clock2
Clock1
VW
Master Clock Circuit
3
Modulator
gm
gm
™ MODULATOR CIRCUIT
Vcrs1
Slave Circuit 1
Slave Circuit 2
S
R
Master
S
R
12
Clock
Q
Q
PWM1
PWM2
Sequencer
Phase
Phase1
Phase2
Hysteretic
Window
L1
I
L2
I
L1
L2
ISL62882, ISL62882B
Clock1
Clock2
Vo
Co
The ISL62882 is a multiphase regulator implementing
Intel
1- or 2-phase operation for microprocessor core
applications. It uses Intersil patented R
Ripple Regulator™) modulator. The R
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. Figure 5 conceptually shows the
ISL62882 multiphase R
6 shows the operation principles.
A current source flows from the VW pin to the COMP pin,
creating a voltage window set by the resistor between
the two pins. This voltage window is called VW window in
the following discussion.
Inside the IC, the modulator uses the master clock circuit
to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor C
current source equal to g
C
between the VW and COMP voltages. It resets to VW
when it hits COMP, and generates a one-shot master
clock signal. A phase sequencer distributes the master
clock signal to the slave circuits. If the ISL62882 is in
2-phase mode, the master clock signal will be distributed
to Phases 1 and 2, and the Clock1 and Clock2 signals will
be 180° out-of-phase. If the ISL62882 is in 1-phase
mode, the master clock signal will be distributed to
Phases 1 only and be the Clock1 signal.
Each slave circuit has its own ripple capacitor C
voltage mimics the inductor ripple current. A g
amplifier converts the inductor voltage into a current
source to charge and discharge C
turns on its PWM pulse upon receiving the clock signal,
and the current source charges C
FIGURE 7. R
rm
Master
Clock1
Clock2
PWM1
PWM2
®
voltage V
Clock
Vcrm
IMVP-6.5™ protocol. It can be programmed for
PRINCIPLES IN LOAD INSERTION
RESPONSE
3
crm
™ MODULATOR OPERATION
Vcrs2
is a sawtooth waveform traversing
Vcrs1
COMP
VW
3™
m
VW
V
modulator circuit, and Figure
o
, where g
rs
rs
. When C
. The slave circuit
3™
m
3™
is a gain factor.
modulator
rm
(Robust
rs
voltage
with a
m
rs
, whose
FN6890.3