ISL95870HRUZ-T Intersil, ISL95870HRUZ-T Datasheet - Page 25

• Manufacturer Part Number: ISL95870HRUZ-T
• Description: IC CTRLR PWM 1PHASE GPU 16UTQFN
• Manufacturer: Intersil

Specifications of ISL95870HRUZ-T

• Applications: Controller, GPU Core Power
• Voltage - Input: 3.3 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 V ~ 5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

capacitors between the MOSFETs and the load. High
frequency output decoupling capacitors (ceramic) should
be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any
internal planes. Place the components in such a way that
the area under the IC has less noise traces with high
dV/dt and di/dt, such as gate signals and phase node
signals.
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to
the IC. In particular, the PVCC decoupling capacitor
should have a very short and wide connection to the
PGND pin. The VCC decoupling capacitor should be
referenced to GND pin.
EN, PGOOD, VID0, VID1, AND FSEL PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
FIGURE 21. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
HIGH-SIDE
MOSFETS
GROUND
VIAS TO
PLANE
PHASE
NODE
VOUT
GND
VIN
25
OUTPUT
CAPACITORS
ISL95870, ISL95870A, ISL95870B
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
OCSET AND VO PINS
The current-sensing network consisting of R
and C
accurate measurement of the DCR voltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
FB, SREF, SET0, SET1, SET2, AND RTN PINS
The input impedance of these pins is high, making it
critical to place the components connected to these pins
as close as possible to the IC.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt
and high di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when
LGATE goes low. Ideally, route the trace from the LGATE
pin in parallel with the trace from the PGND pin, route
the trace from the UGATE pin in parallel with the trace
from the PHASE pin. In order to have more accurate
zero-crossing detection of inductor current, it is
recommended to connect Phase pin to the drain of the
low-side MOSFETs with Kelvin connection. These pairs of
traces should be short, wide, and away from other traces
with high input impedance; weak signal traces should not
be in proximity with these traces on any layer.
SEN
needs to be connected to the inductor pads for
December 22, 2009
OCSET
, R
FN6899.0
O
,