ISL80101AIRAJZ Intersil, ISL80101AIRAJZ Datasheet - Page 9

• Manufacturer Part Number: ISL80101AIRAJZ
• Description: IC REG LDO ADJ 1A 10DFN
• Manufacturer: Intersil

Specifications of ISL80101AIRAJZ

• Regulator Topology: Positive Adjustable
• Voltage - Output: 0.8 V ~ 5 V
• Voltage - Input: 2.2 V ~ 6 V
• Voltage - Dropout (typical): 0.09V @ 1A
• Number Of Regulators: 1
• Current - Output: 1A (Max)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-VFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -

Table 2 shows the recommended C
output voltage and ceramic C
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the V
longer than 0.5cm.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 7)” on page 4.
The power dissipation can be calculated by using Equation 8:
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
maximum allowable power dissipation, as shown in Equation 9:
θ
For safe operation, ensure that the power dissipation P
calculated from Equation 8, is less than the maximum allowable
power dissipation P
The DFN package uses the copper area on the PCB as a heat-sink.
The EPAD of this package must be soldered to the copper plane
(GND plane). Figure 13 shows a curve for the θ
package for different copper area sizes.
P
P
JA
D
D MAX
(
is the junction-to-ambient thermal resistance.
TABLE 2. RECOMMENDED C
=
V
5.0
3.3
2.5
1.8
1.5
1.5
1.2
1.2
1.0
0.8
(V)
OUT
(
V
)
IN
=
–
(
V
T
OUT
J MAX
(
)
(k
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
2.61
R
×
IN
Ω
)
3
D(MAX)
I
–
OUT
)
and GND pins of the LDO with PCB traces no
T
A
) θ
+
⁄
V
.
IN
JA
PB
OUT
0.287
0.464
0.649
×
1.87
1.87
4.32
(k
2.61
1.0
1.3
1.3
R
9
I
Ω
GND
FOR DIFFERENT V
2
.
)
PB
, R
3 and
A(MAX)
C
(
µ
10
10
10
10
10
22
22
47
47
47
OUT
J(MAX)
JA
F)
R
2
OUT
of the DFN
determine the
for different
AND C
and the
D
,
C
100
100
150
120
270
220
220
ISL80101A
(pF)
OUT
82
82
68
PB
(EQ. 8)
(EQ. 9)
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the die
temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
General PowerPAD Design Considerations
Figure 14 shows the recommended use of vias on the thermal pad
to remove heat from the IC. This typical array populates the thermal
pad footprint with vias spaced three times the radius distance from
the center of each via. Small via size is advisable, but not to the
extent that solder reflow becomes difficult.
All vias should be connected to the pad potential, with low thermal
resistance for efficient heat transfer. Complete connection of the
plated-through hole to each plane is important. It is not
recommended to use “thermal relief” patterns to connect the vias.
FIGURE 13. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
46
44
42
40
38
36
34
2
4
THERMAL VIAS θ
AREA ON PCB
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
6
FIGURE 14. PCB VIA PATTERN
8
10
JA
12
vs EPAD-MOUNT COPPER LAND
14
16
18
20
February 24, 2011
2
22
FN7712.2
24