ISL9305IRTHWLNCZ-T Intersil, ISL9305IRTHWLNCZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL9305IRTHWLNCZ-T
• Description: IC PMIC 800MA 3MHZ 16TQFN
• Manufacturer: Intersil

Specifications of ISL9305IRTHWLNCZ-T

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 3: 0.9 V ~ 3.3 V, 350mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Undervoltage Lockout (UVLO)
An undervoltage lockout (UVLO) circuit is provided on ISL9305H. The
UVLO circuit block can prevent abnormal operation in the event that
the supply voltage is too low to guarantee proper operation. The
UVLO on VINDCD1 is set for a typical 2.2V with 100mV hysteresis.
VINLDO1 and VINLDO2 are set for a typical 1.4V with 50mV
hysteresis. When the input voltage is sensed to be lower than the
UVLO threshold, the related channel is disabled.
DCDPG (DCD Power-Good)
ISL9305H offers an open-drain Power-Good signal with
programmable delay time for monitoring the converters DCD1
and DCD2 output voltages status.
When both DCD1 and DCD2 are enabled and their output voltages
are within the power-good window, an internal power-good signal is
issued to turn off the open-drain MOSFET so the DCDPG pin voltage
can be externally pulled high after a programmed delay time. If
either DCD1 or DCD2 output voltages or both of them are not within
the power-good window, the DCDPG outputs an open-drain logic low
signal after the programmed delay time.
When there is only one DCD converter (either DCD1 or DCD2) is
enabled, then the DCDPG only indicates the status of this active
DCD converter. For example, if only DCD1 converter is enabled
and DCD2 converter is disabled, when DCD1 output is within the
power-good window, internal power-good signal will be issued to
turn off the open-drain MOSFET so the DCDPG pin voltage is
externally pulled high after the programmed delay time. If output
voltage of DCD1 is outside the power-good window, the DCDPG
outputs an open-drain logic low signal after the programmed
delay time. It is similar when only DCD2 is enabled and DCD1 is
disabled. When both converters are disabled, DCDPG always
outputs the open-drain logic low signal.
Low Dropout Operation
Both DCD1 and DCD2 converters feature the low dropout operation
to maximize the battery life. When the input voltage drops to a level
that the converter can no longer operate under switching regulation
to maintain the output voltage, the P-Channel MOSFET is completely
turned on (100% duty cycle). The dropout voltage under such a
condition is the product of the load current and the ON-resistance of
the P-Channel MOSFET. Minimum required input voltage V
such condition is the sum of output voltage plus the voltage drop
across the inductor and the P-Channel MOSFET switch.
8
IN
ISL9305H
under
Active Output Voltage Discharge For
DCD1/DCD2
The ISL9305H offers a feature to actively discharge the output
voltage of DCD1 and DCD2 via an internal bleeding resistor
(typical 115Ω) when the channel is disabled. This feature is
enabled by default, but can be individually outputs can be
disabled through programming the control bit in
DCD_PARAMETER register.
Thermal Shutdown
The ISL9305H provides built-in thermal protection function with
thermal shutdown threshold temperature set at +155°C with
+25°C hysteresis (typical). When the die temperature is sensed
to reach +130°C, the regulator is completely shut down and as
the temperature is sensed to drop to +105°C (typical), the device
resumes normal operation starting from the soft-start.
I
The ISL9305H offers an I
SCLK for the serial clock and SDAT for serial data respectively.
According to the I
the clock and data signals to connect to a positive supply. When the
ISL9305 and the host use different supply voltages, the pull-up
resistors should be connected to the higher voltage rail.
Signal timing specifications should satisfy the standard I
specification. The maximum bit rate is 400kb/s and more details
regarding the I
I
The ISL9305H serves as a slave device and the 7-bit default chip
address is 1101000, as shown in Figure 4. According to the I
specifications, here the value of Bit 0 determines the direction of
the message (“0” means “write” and “1” means “read”).
I
Figures 5, 6, and 7 show three typical I
2
2
2
C Slave Address
C Protocol
C Compatible Interface
BIT 7
MSB
1
BIT 6
1
2
C specifications can be found from Philips.
2
FIGURE 4. I
C specifications, a pull-up resistor is needed for
BIT 5
0
2
C compatible interface, using two pins:
BIT 4
1
2
C SLAVE ADDRESS
BIT 3
0
2
C-bus transaction protocols.
BIT 2
0
BIT 1
0
November 8, 2010
BIT 0
LSB
R/W
2
FN7724.0
C bus
2
C