LM25066APSQE/NOPB National Semiconductor, LM25066APSQE/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM25066APSQE/NOPB
• Description: IC CTLR PM HOTSWAP 24-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM25066APSQE/NOPB

• Applications: Base Station-Networking Line Cards, Servers
• Current - Supply: 5.8mA
• Voltage - Supply: 2.9 V ~ 17 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Input Voltage: 17V
• Internal Switch: No
• Supply Voltage Range: 2.9V To 5.5V
• Rohs Compliant: Yes
• Digital Ic Case Style: LLP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM25066APSQE/NOPBTR

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Power Up Sequence
The VIN operating range of the LM25066A is +2.9V to +17V,
with a transient capability to +20V. Referring to
Figure
N-channel MOSFET (Q
pull-down current at the GATE pin. The strong pull-down cur-
rent at the GATE pin prevents an inadvertent turn-on as the
MOSFET’s gate-to-drain (Miller) capacitance is charged. Ad-
ditionally, the TIMER pin is initially held at ground. When the
VIN voltage reaches the POR threshold the insertion time be-
gins. During the insertion time, the capacitor at the TIMER pin
(C
by a 2 mA pull-down current at the GATE pin regardless of
the input voltage. The insertion time delay allows ringing and
transients at VIN to settle before Q
time ends when the TIMER pin voltage reaches 1.7V. C
then quickly discharged by an internal 2 mA pull-down cur-
rent. The GATE pin then switches on Q
the UVLO threshold. If V
the end of the insertion time, Q
GATE pin charge pump sources 22 µA to charge the gate
capacitance of Q
with respect to ground, is limited by an internal 18.8V zener
diode.
T
) is charged by a 5.5 µA current source, and Q
2, as the voltage at VIN initially increases, the external
1
. The maximum voltage at the GATE pin,
1
SYS
) is held off by an internal 190 mA
is above the UVLO threshold at
1
switches on at that time. The
1
is enabled. The insertion
1
when V
FIGURE 1. Typical Application Circuit
Figure
SYS
1
is held off
exceeds
1, and
T
is
14
As the voltage at the OUT pin increases, the LM25066A mon-
itors the drain current and power dissipation of MOSFET Q
In-rush current limiting and/or power limiting circuits actively
control the current delivered to the load. During the in-rush
limiting interval (t
current source charges C
input current reduce below their respective limiting thresholds
before the TIMER pin reaches 1.7V the 90 µA current source
is switched off, and C
current sink (t
complete when the voltage at the OUT pin increases to within
1.3V of the input voltage and the PGD pin switches high.
If the TIMER pin voltage reaches 1.7V before in-rush current
limiting or power limiting ceases during t
and Q
a complete description of the fault mode.
The LM25066A will pull the SMBA pin low after the input volt-
age has exceeded its POR threshold to indicate that the
volatile memory and device settings are in their default state.
The CONFIG_PRESET bit within the STATUS_MFR_SPE-
CIFIC register (80h) indicates default configuration of warning
thresholds and device operation and will remain high until a
CLEAR_FAULTS command is received.
1
is turned off. See the Fault Timer & Restart section for
3
in
2
Figure
in
Figure
T
is discharged by the internal 2.8 µA
T
2). The in-rush limiting interval is
. If Q
2) an internal 90 µA fault timer
1
’s power dissipation and the
2
, a fault is declared
30146011
1
.