JS28F640J3D75D NUMONYX, JS28F640J3D75D Datasheet - Page 45

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JS28F640J3D75D

Manufacturer Part Number
JS28F640J3D75D
Description
IC FLASH 64MBIT 75NS 56TSOP
Manufacturer
NUMONYX
Datasheet

Specifications of JS28F640J3D75D

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8Mx8, 4Mx16)
Speed
75ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TFSOP (0.551", 14.00mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
876722
876722TR
876722TR
JS28F640J3D75 S L8YP
JS28F640J3D75DTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
JS28F640J3D75D
Manufacturer:
RENESAS
Quantity:
5
Numonyx™ Embedded Flash Memory (J3 v. D)
9.7.6
Figure 20: Protection Register Memory Map
Note:
Table 28: Word-Wide Protection Register Addressing
November 2007
308551-05
Note:
LOCK
Word
A0 is not used in x16 mode when accessing the protection register map. See
is used, see
0
1
2
3
4
5
6
7
All address lines not specified in the above table must be 0 when accessing the Protection Register (i.e., A[MAX:9] = 0.)
Locking the OTP Protection Register
The user-programmable segment of the Protection Register is lockable by programming
Bit 1 of the Protection Lock Register (PLR) to 0. Bit 0 of this location is programmed to
0 at the Numonyx factory to protect the unique device number. Bit 1 is set using the
Protection Program command to program “0xFFFD” to the PLR. After these bits have
been programmed, no further changes can be made to the values stored in the
Protection Register. Protection Program commands to a locked section will result in a
Status Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.
Table 29
Factory
Factory
Factory
Factory
User
User
User
User
Both
Use
for x8 addressing.
Address
Word
0x88
0x85
0x84
0x81
0x80
A8
1
1
1
1
1
1
1
1
1
15 14 13 12 11 10 9
128-Bit Protection Register 0
A[24:1]: 256 Mbit
A[23:1]: 128 Mbit
(Factory-Programmed)
(User-Programmable)
A7
0
0
0
0
0
0
0
0
0
64-bit Segment
64-bit Segment
Lock Register 0
8
7
A6
0
0
0
0
0
0
0
0
0
6
5
4
3
A[22:1]: 64 Mbit
A[21:1]: 32 Mbit
A5
2
0
0
0
0
0
0
0
0
0
1
0
Table 28
A4
0
0
0
0
0
0
0
0
1
for x16 addressing. If x8 mode A0
A3
0
0
0
0
1
1
1
1
0
A2
0
0
1
1
0
0
1
1
0
Datasheet
A1
0
1
0
1
0
1
0
1
0
45

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