PC28F640J3D75A NUMONYX, PC28F640J3D75A Datasheet - Page 47
![IC FLASH 64MBIT 75NS 64EZBGA](/photos/7/24/72452/pc28f640j3d75_875776_sml.jpg)
PC28F640J3D75A
Manufacturer Part Number
PC28F640J3D75A
Description
IC FLASH 64MBIT 75NS 64EZBGA
Manufacturer
NUMONYX
Datasheet
1.PC28F640J3D75E.pdf
(68 pages)
Specifications of PC28F640J3D75A
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (8Mx8, 4Mx16)
Speed
75ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
875776
875776
PC28F640J3D75 875776
875776
PC28F640J3D75 875776
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F640J3D75A
Manufacturer:
Numonyx
Quantity:
288
Company:
Part Number:
PC28F640J3D75A
Manufacturer:
MICRON
Quantity:
878
Company:
Part Number:
PC28F640J3D75A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Numonyx™ Embedded Flash Memory (J3 v. D)
10.0
Table 30: Command Bus Operations for Numonyx™ Embedded Flash Memory (J3 v. D)
Notes:
1.
2.
3.
4.
November 2007
308551-05
In case of 256 Mb device (2x128), the command should be issued to the base address of the die
In case of 256 Mb device (2x128), the command sequence must be repeated for each die at its base address
In case of 256 Mb device (2x128), keep the second cycle to the same address. (i.e. Do not toggle A24 for the second
cycle)
In case of 256 Mb device (2x128), the second cycle must be writtne to the Block Address and Offset address to be
programmed
Program Enhanced Configuration Register
Program OTP Register
Clear Status Register
Program STS Configuration Register
Read Array
Read Status Register
Read Identifier Codes (Read Device Information)
CFI Query
Word/Byte Program
Buffered Program
Block Erase
Program/Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Device Command Codes
The list of all applicable commands are included here one more time for the
convenience.
Command
Register Data
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Device Address
Block Address
Block Address
Word Address
Address Bus
Setup Write Cycle
1,2
1
1
1
2
2
2
2
2
1
1
1
2
1
2
Data Bus
0040h/
00D0h
0060h
00C0h
0050h
00B8h
0070h
0090h
0098h
0010h
00E8h
0020h
00B0h
0060h
0060h
00FFh
Device Address
Device Address
Device Address
Device Address
Address Bus
Register Offset
Block Address
Block Address
Register Data
Confirm Write Cycle
---
---
---
---
---
---
---
3
4
Register Data
Register Data
Array Data
Data Bus
00D0h
00D0h
00D0h
0004h
0001h
Datasheet
---
---
---
---
---
---
---
47