PC28F640P30B85A NUMONYX, PC28F640P30B85A Datasheet - Page 47
![IC FLASH 64MBIT 85NS 64EZBGA](/photos/7/29/72901/pc28f640p30b85_873919_sml.jpg)
PC28F640P30B85A
Manufacturer Part Number
PC28F640P30B85A
Description
IC FLASH 64MBIT 85NS 64EZBGA
Manufacturer
NUMONYX
Series
StrataFlash™r
Datasheet
1.RD48F4400P0VBQEJ.pdf
(97 pages)
Specifications of PC28F640P30B85A
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
64M (4M x 16)
Speed
85ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
873919
873919
PC28F640P30B85
873919
PC28F640P30B85
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PC28F640P30B85A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
P30
11.2.8
11.2.9
11.2.10
11.3
August 2008
Order Number: 306666-12
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word-length boundaries or cross word-length
boundaries. When BW is set, burst wrapping does not occur (default). When BW is
cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device-row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start
address is at the end of a 4-word boundary, the worst case output delay is one clock
cycle less than the first access Latency Count. This delay can take place only once, and
doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT
informs the system of this delay when it occurs.
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
End of Word Line (EOWL) Considerations
When performing synchronous burst reads with BW set (no wrap) and DH reset (1 clock
cycle), an output “delay” requiring additions clock Wait States may occur when the
burst sequence crosses its first device-row (16-word) boundary. The delay would take
place only once, and will not occur if the burst sequence does not cross a device-row
boundary. The WAIT signal informs the system of this delay when it occurs. If the burst
sequence’s start address is 4-word aligned (i.e. 0x00h, 0x04h, 0x08h, 0x0Ch) then no
delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h,
0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States required) will be
one clock cycle less than the first access Latency Count (LC-1) when crossing the first
device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalignments may require
wait states depending upon the LC setting and the starting address alignment. For
example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but
the same LC setting of 3 with a starting address of 0xFE would require 1 wait state
when crossing the first device row boundary.
One-Time-Programmable (OTP) Registers
The device contains 17 one-time-programmable (OTP) registers that can be used to
implement system security measures and/or device identification. Each OTP register
can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. When programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see
“OTP register map” on page
The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR
bits cannot be erased. Each OTP Register can be accessed multiple times to program
individual bits, as long as the register remains unlocked.
Table 22, “Burst Sequence Word Ordering” on page
48).
46). When a burst
Figure 16,
Datasheet
47