AT25DF081A-SH-T Atmel, AT25DF081A-SH-T Datasheet
AT25DF081A-SH-T
Specifications of AT25DF081A-SH-T
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AT25DF081A-SH-T Summary of contents
Page 1
... Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 208-mil wide) – 8-pad Ultra Thin DFN ( 0.6mm) 8-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory Atmel AT25DF081A 8715B–SFLSH–8/10 ...
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... EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF081A have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
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... Hold operation. The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used. However recommended that the HOLD pin also be externally connected to V whenever possible. 8715B–SFLSH–8/10 Atmel AT25DF081A Asserted for more details on protection CC State ...
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... Block Diagram Figure 3-1. Block Diagram CS SCK INTERFACE CONTROL SI (SIO) LOGIC SO (SOI) WP HOLD Atmel AT25DF081A 4 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be Figure 2-2. VCC 8 HOLD 7 SCK 6 SI (SIO) 5 CONTROL AND ...
Page 5
... Atmel AT25DF081A ® AT25DF081A can be erased in four levels of Page Program Detail 1-256 Byte Block Address Page Program Range (02h Command) 0FFFFFh – 0FF000h 256 Bytes 0FEFFFh – 0FE000h 256 Bytes 0FDFFFh – 0FD000h 256 Bytes 0FCFFFh – ...
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... AT25DF081A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25DF081A via the SPI bus which is com- prised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO). ...
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... Read Status Register Write Status Register Byte 1 Write Status Register Byte 2 Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down 8715B–SFLSH–8/10 Atmel AT25DF081A Clock Opcode Frequency 1Bh 0001 1011 Up to 100MHz 0Bh 0000 1011 Up to 85MHz ...
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... Read Array – 1Bh Opcode SCK OPCODE MSB MSB HIGH-IMPEDANCE SO Atmel AT25DF081A 8 , and the 03h opcode can be used for lower frequency CLK . The 1Bh opcode allows the highest read performance pos- RDLF should be reserved to systems employing the Atmel RapidS CLK ADDRESS BITS A23-A0 DON'T CARE ...
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... Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-3. Read Array – 03h Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ ADDRESS BITS A23- MSB ADDRESS BITS A23- MSB Atmel AT25DF081A DON'T CARE MSB DATA BYTE MSB DATA BYTE MSB MSB MSB 9 ...
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... Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-4. Dual-Output Read Array SCK OPCODE SIO MSB HIGH-IMPEDANCE SO Atmel AT25DF081A ADDRESS BITS A23- ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. 8715B–SFLSH–8/10 “Write Enable” on page only programming a single byte “Sector Lockdown” on page 25), then the Byte/Page Program command will not Atmel AT25DF081A 17) to set the Write Enable “Protect Sector” time ...
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... Figure 8-1. Byte Program SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 8-2. Page Program SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A ADDRESS BITS A23- MSB ADDRESS BITS A23-A0 DATA IN BYTE MSB MSB DATA MSB DATA IN BYTE MSB D D 8715B–SFLSH–8/10 ...
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... If a programming error arises, it will be indicated by the EPE bit in the Status Register. 8715B–SFLSH–8/10 “Write Enable” on page 17) to set the Write Enable Latch (WEL) bit of the Sta only programming a single byte “Sector Lockdown” on page 25), then the Byte/Page Program command will not Atmel AT25DF081A “Protect Sector” time ...
Page 14
... Figure 8-3. Dual-Input Byte Program SCK OPCODE MSB HIGH-IMPEDANCE SOI Figure 8-4. Dual-Input Page Program SCK OPCODE MSB HIGH-IMPEDANCE SOI Atmel AT25DF081A ADDRESS BITS A23- MSB ADDRESS BITS A23- MSB INPUT DATA BYTE MSB INPUT INPUT INPUT DATA BYTE 1 DATA BYTE 2 ...
Page 15
... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop- erly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-5. Block Erase SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ ADDRESS BITS A23- MSB Atmel AT25DF081A . BLKE ...
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... The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase prop- erly erase error occurs, it will be indicated by the EPE bit in the Status Register. Figure 8-6. Chip Erase SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A 16 . CHPE 8715B–SFLSH–8/10 ...
Page 17
... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ Atmel AT25DF081A 17 ...
Page 18
... CS pin is deasserted, and the CS pin must be deas- serted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-2. Write Disable SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A 8715B–SFLSH–8/10 ...
Page 19
... Protect Sector command will be ignored, and the device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-3. Protect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ ADDRESS BITS A23- MSB Atmel AT25DF081A ...
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... WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. Figure 9-4. Unprotect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A 20 Table 9-1 for Sector Protection Register values). Every physical sector ADDRESS BITS A23- ...
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... Global Unprotect – all Sector Protection Registers reset change to current protection. No change to current protection. No change to current protection. Global Protect – all Sector Protection Registers set to 1 Atmel AT25DF081A “Write Status Register Byte 1” on page 35 details the conditions necessary for a Global Pro- New SPRL ...
Page 22
... WP pin and the sector protection status. Please refer to details on the Status Register format and what values can be read for bits five, four, three, and two. Atmel AT25DF081A 22 Bit Protection Operation No change to the current protection level ...
Page 23
... Status Register” on page 31 Figure 9-5. Read Sector Protection Register SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/10 , the first byte of data output will not be valid. Therefore, if operating at clock fre- CLK for more details ADDRESS BITS A23- MSB Atmel AT25DF081A DATA BYTE MSB MSB “Read 23 ...
Page 24
... Locking 0 0 Hardware 0 1 Locked 1 0 Software 1 1 Locked Atmel AT25DF081A 24 Sector Protection Register ( SPRL Change Allowed Sector Protection Registers Unlocked and modifiable using the Protect and Unprotect Can be modified from Sector commands. Global Protect and Unprotect can also be performed. Locked in current state. Protect and Unprotect Sector Locked commands will be ignored ...
Page 25
... WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been deasserted. 8715B–SFLSH–8/10 36). To issue the Sector Lockdown command, the below). If the Sector Lockdown command is disabled or if the sector lockdown Atmel AT25DF081A 25 ...
Page 26
... When the device aborts the Freeze Sector Lockdown State operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. Figure 10-2. Freeze Sector Lockdown State SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A ADDRESS BITS A23-A0 CONFIRMATION BYTE ...
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... Figure 10-3. Read Sector Lockdown Register SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/10 , the first byte of data output will not be valid. Therefore, if operating at clock fre- CLK ADDRESS BITS A23- MSB Atmel AT25DF081A DON'T CARE MSB DATA BYTE MSB MSB 27 ...
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... OTP Security Register will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and should take place in a time of t gramming of the OTP Security Register. Atmel AT25DF081A 28 ® and will contain a unique value for each device. The factory pro- ...
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... The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the con- tents of the buffer will be altered from its previous state when this command is issued. Figure 10-4. Program OTP Security Register SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ ADDRESS BITS A23- MSB MSB Atmel AT25DF081A DATA IN BYTE 1 DATA IN BYTE MSB ...
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... Figure 10-5. Read OTP Security Register SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A read the OTP Security Register, the CS pin must first be asserted and MAX ADDRESS BITS A23- ...
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... Atmel AT25DF081A Description Sector Protection Registers are unlocked (default) Sector Protection Registers are locked Reserved for future use Erase or program operation was successful Erase or program error detected WP is asserted WP is deasserted All sectors are software unprotected (all Sector Protection Registers are 0) Some sectors are software protected ...
Page 32
... The EPE bit will not be set if an erase or program operation aborts for any reason such as an attempt to erase or program a protected region or a locked down sector or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated after every erase and program operation. Atmel AT25DF081A 32 (2) ...
Page 33
... The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the RSTE bit will remain in that state until it is modified using the Write Status Register Byte 2 command or until the device has been power cycled. The Reset command itself will not change the state of the RSTE bit. 8715B–SFLSH–8/10 Atmel AT25DF081A 33 ...
Page 34
... To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. Figure 11-1. Read Status Register SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A STATUS REGISTER ...
Page 35
... Figure 11-2. Write Status Register Byte SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/10 Table 11-3). Any additional data bytes that are sent to the device will be ignored. When Bit 5 Bit 4 Bit 3 Global Protect/Unprotect STATUS REGISTER IN BYTE MSB Atmel AT25DF081A “Global Protect/Unprotect” Bit 2 Bit 1 Bit ...
Page 36
... RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state. Table 11-4. Write Status Register Byte 2 Format Bit 7 Bit Figure 11-3. Write Status Register Byte SCK OPCODE MSB HIGH-IMPEDANCE SO Atmel AT25DF081A 36 Bit 5 Bit 4 Bit 3 X RSTE SLE STATUS REGISTER IN BYTE ...
Page 37
... The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. Figure 12-1. Reset SCK OPCODE MSB HIGH-IMPEDANCE SO 8715B–SFLSH–8/ CONFIRMATION BYTE MSB Atmel AT25DF081A . RST 37 ...
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... Extended Device Information (EDI) String Length 5 [Optional to read] EDI Byte 1 Table 12-2. Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Manufacturer Family Code Device ID (Part Sub Code Device ID (Part Atmel AT25DF081A 38 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JEDEC Assigned Code Density Code Product Version Code ...
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... The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. 8715B–SFLSH–8/10 MANUFACTURED ID DEVICE ID DEVICE ID BYTE 1 BYTE 2 shown for SI and SO represents one byte (8 bits) Atmel AT25DF081A EDI EDI STRING LENGTH DATA BYTE 1 39 ...
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... Deep Power- Down mode. Figure 12-4. Resume from Deep Power-Down SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current Atmel AT25DF081A 40 t EDPD Deep Power-Down Mode Current t RDPD ...
Page 41
... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 12-5. Hold Mode CS SCK HOLD 8715B–SFLSH–8/10 Hold Hold Atmel AT25DF081A Hold 41 ...
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... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host con- troller should clock its data out on the rising edge of SCK in order to give the AT25DF081A a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
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... Max 50MHz 0mA; OUT Max 33MHz 0mA; OUT Max 20MHz 0mA; OUT Max Max Max CMOS levels CMOS levels OUT 0 1.6mA Min -100µ Min Atmel AT25DF081A -40°C to 85°C 2.7V to 3.6V Typ Max Units 25 50 µ µ µA 1 µ ...
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... Chip Select High to Standby Mode RDPD t Reset Time RST Notes: 1. Not 100% tested (value guaranteed by design and characterization) 2. 15pF load at frequencies above 70MHz, 30pF otherwise 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1 Atmel AT25DF081A 44 Min Max 100 Min Max 4 ...
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... R F 14.9 Output Test Load DEVICE UNDER TEST 15pF (frequencies above 70MHz) or 30pF 8715B–SFLSH–8/10 4-Kbytes 32-Kbytes 64-Kbytes to Chip Select Low Time MEASUREMENT CC LEVEL Atmel AT25DF081A Min Typ Max Units 1.0 3 µs 50 200 250 600 ms 400 950 16 28 sec 200 500 µ ...
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... HIGH-IMPEDANCE SO Figure 15-2. Serial Output Timing CS SCK Figure 15-3. WP Timing for Write Status Register Byte 1 Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER BYTE 1 OPCODE HIGH-IMPEDANCE SO Atmel AT25DF081A 46 t CSLH t CLKH CLKL t DH LSB t CLKH WPH LSB OF WRITE STATUS REGISTER ...
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... Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO 8715B–SFLSH–8/ HHH HLS t HLH t HLS t HLH t HHQX Atmel AT25DF081A t HHS t HHS 47 ...
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... AT25DF081A-MH-T AT25DF081A-SSH-B 8S1 AT25DF081A-SSH-T AT25DF081A-SH-B 8S2 AT25DF081A-SH-T Note: The shipping carrier option code is not marked on the devices. 8MA1 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.208” ...
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... E E2 Option A 1 Pin #1 Notch (0.20 R) (Option TITLE 8MA1, 8-pad ( 0.6mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) Atmel AT25DF081A C Side View Pin #1 Chamfer (C 0.35) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A 0.45 0.55 A1 ...
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... JEDEC SOIC TOP VIEW TOP VIEW e e SIDE VIEW SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF081A TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull ...
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... Package Drawing Contact: packagedrawings@atmel.com 8715B–SFLSH–8/ Top View Side View TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) Atmel AT25DF081A End View q q COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX 2.16 A 1.70 A1 0.05 0. ...
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... Revision History Doc. Rev. Date 8715B 08/2010 8715A 06/2010 Atmel AT25DF081A 52 Comments Change t Max from Parameters RDPD Initial document release 8715B–SFLSH–8/10 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...