AT24C64D-MAHM-T Atmel, AT24C64D-MAHM-T Datasheet - Page 6
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AT24C64D-MAHM-T
Manufacturer Part Number
AT24C64D-MAHM-T
Description
IC EEPROM SER 64K 2-WIRE 8UDFN
Manufacturer
Atmel
Datasheet
1.AT24C64D-SSHM-T.pdf
(26 pages)
Specifications of AT24C64D-MAHM-T
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz, 1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT24C64D-MAHM-T
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
4.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (refer to
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (refer to
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire part can be protocol
reset by following these steps:
The device is ready for next communication after above steps have been completed.
Figure 4-1.
• Upon power-up
• After the receipt of the Stop bit and the completion of any internal operations.
• Create a start bit condition
• Clock nine cycles
• Create another start bit followed by stop bit condition as shown below.
Atmel AT24C32D/64D
SDA
SCL
Software Reset
Start bit
“Start and Stop Definition”
®
1
AT24C32D/64D features a low power standby mode which is enabled:
2
Dummy Clock Cycles
3
diagram).
“Data Validity”
8
“Start and Stop Definition”
diagram). Data changes during SCL
9
Start bit
8717B–SEEPR–6/10
diagram).
Stop bit