MR25H256CDC EverSpin Technologies Inc, MR25H256CDC Datasheet - Page 4

• Manufacturer Part Number: MR25H256CDC
• Description: IC MRAM 256KBIT 40MHZ 8DFN
• Manufacturer: EverSpin Technologies Inc

Specifications of MR25H256CDC

• Format - Memory: RAM
• Memory Type: MRAM (Magnetoresistive RAM)
• Memory Size: 256K (32K x 8)
• Speed: 40MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 819-1015

Everspin Technologies © 2010
2. SPI COMMUNICATIONS PROTOCOL
MR25H256 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The
memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS
falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Status Register
Instruction Description
WREN
WRDI
RDSR
WRSR
READ
WRITE
SLEEP
WAKE
Bit 7
SRWD
The status register consists of the 8 bits listed in table 2.1. As seen in table 2.2, the Status Register Write
Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide
hardware memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected
as described in table 2.3. The fast writing speed of MR25H256 does not require write status bits. The state
of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register
are pre-set from the factory in the “0” state.
Bit 6
Don’t Care
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
Bit 5
Don’t Care
Table 2.2 Status Register Bit Assignments
Binary Code
0000
0000
0000 0101
0000 0001
0000
0000 0010
1011 1001
1010 1011
Table 2.1 Command Codes
Bit 4
Don’t Care
0110
0100
0011
4
Bit 3
BP1
Hex Code
06h
04h
05h
01h
03h
02h
B9h
ABh
Document Number: MR25H256 Rev. 2, 4/2010
Bit 2
BP0
Address Bytes Data Bytes
0
0
0
0
2
2
0
0
Bit 1
WEL
MR25H256
0
0
1
1
1 to ∞
1 to ∞
0
0
Bit 0
Don’t Care