NLSX5012DMR2G ON Semiconductor, NLSX5012DMR2G Datasheet

NLSX5012DMR2G

Manufacturer Part Number

NLSX5012DMR2G

Description

IC TRANSLATOR 2BIT MICRO8

Manufacturer

ON Semiconductor

Datasheet

1.NLSX5012DMR2G.pdf (14 pages)

Specifications of NLSX5012DMR2G

Logic Function

Translator, Bidirectional, 3-State

Number Of Bits

Number Of Outputs/channel

Differential - Input:output

No/No

Propagation Delay (max)

10ns

Input Type

Voltage

Output Type

Voltage

Data Rate

100Mbps

Number Of Channels

Voltage - Supply

0.9 V ~ 4.5 V

Operating Temperature

-40°C ~ 85°C

Package / Case

8-MicroPak™

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

NLSX5012DMR2G

Manufacturer:

ON Semiconductor

Quantity:

2 750

Current page: 1 of 14
Download datasheet (155Kb)

NLSX5012

2-Bit 100 Mb/s Configurable

Dual-Supply Level

Translator

bidirectional level translator that does not require a direction control

pin. The I/O V

different power supply rails, V

and the V

allows a logic signal on the V

or a lower logic signal voltage on the V

because V

translators have a restriction that the value of the V

equal to less than (V

the translator to drive high capacitive loads such as most high

frequency EMI filters. Another feature of the NLSX5012 is that each

I/O_V

output.

consumption. The EN pin can be used to disable both I/O ports by

putting them in 3-state which significantly reduces the supply current

from both V

Features

•

Typical Applications

•

Important Information

•

April, 2011 − Rev. 2

The NLSX5012 is a 2-bit configurable dual-supply autosensing

The NLSX5012 offers the feature that the values of the V

The NLSX5012 has high output current capability, which allows

An Output Enable (EN) input is available to reduce the power

for V

Wide V

High 100 pF Capacitive Drive Capability

High−Speed with 140 Mb/s Guaranteed Date Rate

Low Bit−to−Bit Skew

Overvoltage Tolerant Enable and I/O Pins

Non−preferential Power−Up Sequencing

Power−Off Protection

Small packaging: UDFN8, SO−8, Micro8

These are Pb−Free Devices

Mobile Phones, PDAs, Other Portable Devices

ESD Protection for All Pins:

− V

♦

supplies are independent. Design flexibility is maximized

supply. In contrast, the majority of competitive auto sense

HBM (Human Body Model) > 8000 V

and V

may be greater than, equal to, or less than V

and I/O_V

, V

can be set to a value either greater than or less than the

supply rails are configurable from 0.9 V to 4.5 V. This

, V

and V

> 1.8 V

are independent

Operating Range: 0.9 V to 4.5 V

- and I/O V

CCn

. The EN signal is referenced to the V

channel can function as either an input or an

- 0.4) V.

side to be translated to either a higher

-ports are designed to track two

and V

respectively. Both the V

side, and vice-versa.

supply must be

supply.

and

†For information on tape and reel specifications,

NLSX5012MUTAG

NLSX5012DR2G

NLSX5012DMR2G

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Device

ORDERING INFORMATION

VA = Specific Device Code

= Pb−Free Package

http://onsemi.com

= Pb−Free Package

CASE 517AJ

= Date Code

= Pb−Free Package

MU SUFFIX

CASE 846A

DM SUFFIX

= Assembly Location

= Year

= Work Week

CASE 751

D SUFFIX

= Assembly Location

= Wafer Lot

= Year

= Work Week

UDFN8

Micro8

SO−8

(Pb−Free)

Package

UDFN8

Micro8

SO−8

Publication Order Number:

3000/T ape & Reel

2500/T ape & Reel

4000/T ape & Reel

DIAGRAMS

MARKING

Shipping

NLSX5012/D

AE M

SX5012

AYWG

ALYWG

5012

†

Related parts for NLSX5012DMR2G

NLSX5012DMR2G Summary of contents

Page 1

... L CC side, and vice-versa. CC and CC supply must supply NLSX5012MUTAG NLSX5012DR2G NLSX5012DMR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 http://onsemi.com MARKING DIAGRAMS UDFN8 SUFFIX G CASE 517AJ ...

Page 2

NLSX5012 +1.8 V System I I I/ GND OE EN GND Figure 1. Typical Application Circuit 2 ...

Page 3

I GND UDFN8 (Top View) PIN ASSIGNMENT Pins ...

Page 4

MAXIMUM RATINGS Symbol Parameter V High−side DC Supply Voltage CC V Low−side DC Supply Voltage L I −Referenced DC Input/Output Voltage −Referenced DC Input/Output Voltage Enable Control Pin DC Input ...

Page 5

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V I/O V Input HIGH Voltage IHC CC V I/O V Input LOW Voltage ILC CC V I/O V Input HIGH Voltage IHL L V I/O V Input LOW Voltage ILL L V Control Pin ...

Page 6

TIMING CHARACTERISTICS Symbol Parameter t I/O V Rise Time R−VCC CC t I/O V Fall Time F−VCC CC t I/O V Rise Time R− I/O V Fall Time F− I/O V One−Shot OVCC CC Output Impedance ...

Page 7

TIMING CHARACTERISTICS (continued) Symbol Parameter t I/O_V Output Enable Time EN−VCC CC t I/O_V Output Enable Time EN− I/O_V Output Disable Time DIS−VCC CC t I/O_V Output Disable Time DIS−VL L MDR Maximum Data Rate 10. Normal test ...

Page 8

DYNAMIC POWER CONSUMPTION Symbol Parameter Input port MHz, PD_VL L Load V = Output Port Input port MHz, ...

Page 9

STATIC POWER CONSUMPTION (T Symbol Parameter Input port MHz, PD_VL L Load V = Output Port EN = GND (outputs disabled Input port ...

Page 10

NLSX5012 I Source t v I/O V RISE/FALL 90% 50% 10% t PD_VL−VCC I 90% 50% 10% t F−VCC Figure 7. Driving I/O V Test Circuit and Timing L PULSE ...

Page 11

IMPORTANT APPLICATIONS INFORMATION Level Translator Architecture The NLSX5012 auto−sense bi−directional logic voltage level shifting to transfer data in multiple supply voltage systems. These level translators have two supply voltages, V and levels on the input and output ...

Page 12

0.10 C PIN ONE E REFERENCE Ï Ï 0.10 C TOP VIEW (A3 SIDE VIEW e/2 DETAIL (b2 (L2 BOTTOM ...

Page 13

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 14

... A1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein ...

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