FT232HQ-REEL FTDI, Future Technology Devices International Ltd, FT232HQ-REEL Datasheet - Page 27

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FT232HQ-REEL

Manufacturer Part Number
FT232HQ-REEL
Description
IC HS USB TO UART/FIFO 48QFN
Manufacturer
FTDI, Future Technology Devices International Ltd
Datasheet

Specifications of FT232HQ-REEL

Number Of Channels
1, UART
Fifo's
*
Protocol
RS-232, RS-422, RS-485
Voltage - Supply
1.62 V ~ 1.98 V, 2.97 V ~ 3.63 V
With Parallel Port
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
*
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
With Auto Flow Control
-
With Irda Encoder/decoder
-
With Cmos
-
Other names
768-1102-2

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
FT232HQ-REEL
Manufacturer:
FTDI
Quantity:
1 000
Part Number:
FT232HQ-REEL
0
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings
This mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60 MHz
CLKOUT clock for the external system to use.
Note that Asynchronous FIFO mode must be selected in the EEPROM before selecting the Synchronous
FIFO mode in software.
4.4.1 FT245 Synchronous FIFO Read Operation
A read operation is started when the chip drives RXF# low. The external system can then drive OE# low
to turn the data bus drivers around before acknowledging the data with the RD# signal going low. The
first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by
keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will
change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive
RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored.
4.4.2 FT245 Synchronous FIFO Write Operation
A write operation can be started when TXE# is low. WR is brought low when the data is valid. A burst
operation can be done on every clock providing TXE# is still low. The external system must monitor TXE#
and its own WR to check that data has been accepted. Both TXE# and WR must be low for data to be
accepted.
Name
t10
t11
t12
t13
t14
t15
t1
t2
t3
t4
t5
t6
t7
t8
t9
Min
7.5
7.5
7.5
7.5
7.5
7.5
0
0
0
0
0
0
0
0
Copyright © 2011 Future Technology Devices International Limited
16.67
Nom
8.33
8.33
9
9
9
9
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
9.17
Max
9.17
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR# setup time to CLKOUT (WR# low after TXE# low)
RD# setup time to CLKOUT (RD# low after OE# low)
CLKOUT to read DATA valid
OE# to read DATA valid
Write DATA setup time
Write DATA hold time
CLKOUT high period
CLKOUT low period
CLKOUT TO TXE#
CLKOUT to RXF#
OE# setup time
CLKOUT period
WR# hold time
OE# hold time
RD# hold time
Comments
Document No.: FT_000288
Clearance No.: FTDI #199
Datasheet Version 1.2
27

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