MPC8533EVTALFA Freescale Semiconductor, MPC8533EVTALFA Datasheet - Page 1306

• Manufacturer Part Number: MPC8533EVTALFA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTALFA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Glossary
S
Glossary-8
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Sticky bit. A bit that when
Reservation. The processor establishes a reservation on a
Reservation station. A buffer between the dispatch and execute stages that allows
Secondary cache. A cache memory that is typically larger and has a longer access time
Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term ‘set’
Set (n). A subdivision of a cache. Cacheable data can be stored in a given location in one
Set-associative. Aspect of cache organization in which the cache space is divided into
Slave. The device addressed by a master device. The slave is identified in the address
Snooping. Monitoring addresses driven by a bus master to detect the need for coherency
Snoop push. Response to a snooped transaction that hits a modified cache block. The
Stall. An occurrence when an instruction cannot proceed to the next stage.
Superscalar machine. A machine that can issue multiple instructions concurrently from
Supervisor mode. The privileged operation state of a processor. In supervisor mode,
Synchronization. A process to ensure that operations occur strictly
System memory. The physical memory available to a processor.
when it executes an lwarx instruction to read a memory semaphore into a GPR.
instructions to be dispatched even though the results of instructions on which the
dispatched instruction may depend are not available.
than the primary cache. A secondary cache may be shared by multiple devices.
Also referred to as L2, or level-2, cache.
may also be used to generally describe the updating of a bit or bit field.
of the sets, typically corresponding to its lower-order address bits. Because several
memory locations can map to the same location, cached data is typically placed in
the set whose
See
sections, called sets. The cache controller associates a particular main memory
address with the contents of a particular set, or region, within the cache.
tenure and is responsible for supplying or latching the requested data for the
master during the data tenure.
actions.
cache block is written to memory and made available to the snooping device.
a conventional linear instruction stream.
software, typically the operating system, can access all control registers and can
access the supervisor memory space, among other privileged operations.
synchronization.
Set
associative.
cache block
set
must be cleared explicitly.
corresponding to that address was used least recently.
cache block
in
Freescale Semiconductor
order. See
of memory space
Context