STM32F103VFT6 STMicroelectronics, STM32F103VFT6 Datasheet - Page 13

• Manufacturer Part Number: STM32F103VFT6
• Description: MCU ARM CORTEX MCU 768KB 100LQFP
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F103VFT6

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: DMA, Motor Control PWM, PDR, POR, PVD, PWM, Temp Sensor, WDT
• Number Of I /o: 80
• Program Memory Size: 768KB (768K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Processor Series: STM32F101xF
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 36 MHz
• Number Of Programmable I/os: 112
• Number Of Timers: 15
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: STM32F103VF
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

STM32F103xF, STM32F103xG
Figure 2.
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
2. For the USB function to be available, both HSE and PLL must be enabled, with the USBCLK at 48 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
OSC32_OUT
OSC32_IN
64 MHz.
OSC_OUT
OSC_IN
MCO
Clock tree
4-16 MHz
32.768 kHz
HSE OSC
Main
Clock Output
LSE OSC
HSI RC
8 MHz
LSI RC
40 kHz
PLLSRC
MCO
x2, x3, x4
PLLMUL
HSI
..., x16
PLLXTPRE
PLL
/2
/128
LSE
/2
LSI
RTCSEL[1:0]
/2
HSE
Doc ID 16554 Rev 2
PLLCLK
SYSCLK
HSI
PLLCLK
RTCCLK
to Independent Watchdog (IWDG)
HSI
HSE
CSS
SW
SYSCLK
72 MHz
to RTC
max
IWDGCLK
Prescaler
/1, 2..512
AHB
Prescaler
Peripheral clock
enable
Peripheral clock
enable
/1, 1.5
USB
/1, 2, 4, 8, 16
If (APB1 prescaler =1) x1
/1, 2, 4, 8, 16
TIM2,3,4,5,12,13,14,6,7
If (APB2 prescaler =1) x1
TIM1, 8, 9, 10, 11
Peripheral clock
enable
Peripheral clock
enable
/8
Prescaler
Prescaler
72 MHz max
APB1
APB2
Prescaler
/2, 4, 6, 8
Clock
FLITFCLK
to Flash programming interface
Enable
/2
ADC
48 MHz
HSE = High-speed external clock signal
HSI =
LSI =
LSE =
Legend:
I2S3CLK
I2S2CLK
Peripheral clock
enable
Low-speed internal clock signal
High-speed internal clock signal
Low-speed external clock signal
else x2
72 MHz max
else x2
36 MHz max
ADCCLK
Peripheral Clock
Peripheral Clock
Enable
Enable
USBCLK
to USB interface
Peripheral Clock
HCLK
to AHB bus, core,
memory and DMA
Enable
FCLK Cortex
free running clock
to I2S3
to I2S2
to Cortex System timer
Peripheral Clock
Enable
To SDIO AHB interface
FSMCCLK
SDIOCLK
HCLK/2
to TIM1/8
and TIM9/10/11
TIMxCLK
to TIM2/3/4/5/12/13/14
and TIM6/7
TIMxCLK
peripherals to APB2
PCLK1
to APB1
peripherals
PCLK2
to ADC1, 2 or 3
to FSMC
Description
to SDIO
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