STM32F107VCH6 STMicroelectronics, STM32F107VCH6 Datasheet - Page 95

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STM32F107VCH6

Manufacturer Part Number
STM32F107VCH6
Description
IC ARM CORTEX MCU 256KB 100LFBGA
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet

Specifications of STM32F107VCH6

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
80
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
Core
ARM Cortex M3
Featured Product
STM32 Cortex-M3 Companion Products
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32F107VCH6
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F105xx, STM32F107xx
Table 62.
1. SYSCLK is set to be at 72 MHz except in this case where SYSCLK is at 71.88 MHz.
Ethernet only
Ethernet + OTG
Ethernet + OTG
+ basic audio
Ethernet + OTG
+ Audio class
I
OTG only
OTG + basic
audio
OTG + Audio
class I
Audio class I
only
2
S
Application
(1)
(1)
2
S
(1)
2
S
PLL configurations
Table 63
Table
value in
14.7456
14.7456
14.7456
Crystal
(XT1)
MHz
25
25
25
8
8
62.
PREDIV2 PLL2MUL PLLSRC
give the I
NA
NA
/5
/5
/5
/4
/4
/4
PLL2OFF
PLL2OFF
PLL2ON
PLL2ON
PLL2ON
PLL2ON
PLL2ON
PLL2ON
DD
x12
x12
x12
x8
x8
x8
run mode values that correspond to the conditions specified in
PLL2
PLL2
PLL2
PLL2
PLL2
PLL2
XT1
XT1
Doc ID 15274 Rev 5
PREDIV1
/5
/5
/5
/4
/1
/1
/4
/4
PLLON x9
PLLON x9
PLLON x9
PLLON x9
PLLON x9
PLLMUL
PLLON
PLLON
PLLON
x6.5
x6.5
x6.5
prescaler
(PLLVCO
output)
USB
NA
NA
/3
/3
/3
/3
/3
/3
Application block diagrams
PLL3MUL
PLL3OFF
PLL3OFF
PLL3ON
PLL3ON
PLL3ON
PLL3ON
PLL3ON
PLL3ON
x10
x10
x10
x20
x20
x20
clock
input
PLL3
PLL3
PLL3
VCO
VCO
VCO
I2Sn
PLL
PLL
Out
Out
NA
NA
NA
out
MCO (main
PLL3 (RMII)
PLL3 (RMII)
PLL3 (RMII)
must use its
own crystal
ETH PHY
XT1 (MII)
XT1 (MII)
XT1 (MII)
output)
clock
NA
NA
NA
NA
NA
95/101

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