PIC16LF721-I/ML Microchip Technology, PIC16LF721-I/ML Datasheet - Page 136
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PIC16LF721-I/ML
Manufacturer Part Number
PIC16LF721-I/ML
Description
MCU PIC 4K FLASH 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF721-I/ML
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
17
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VFQFN Exposed Pad
Controller Family/series
PIC16LF
No. Of I/o's
18
Ram Memory Size
256Byte
Cpu Speed
16MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF720/721
16.3.2
The following bits are used to configure the AUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
AUSART.
16.3.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master
case of the Sleep mode.
TABLE 16-8:
DS41430A-page 136
INTCON
PIE1
PIR1
RCSTA
TRISC
TXREG
TXSTA
Legend:
Name
are
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave transmission.
SYNCHRONOUS SLAVE MODE
TMR1GIE
TMR1GIF
TRISC7
AUSART Synchronous Slave
Transmit
SPEN
CSRC
Bit 7
GIE
identical
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
TRISC6
Transmission”), except in the
ADIE
Bit 6
PEIE
ADIF
RX9
TX9
(refer
TMR0IE
TRISC5
to
SREN
TXEN
RCIE
RCIF
Bit 5
AUSART Transmit Data Register
Section 16.3.1.2
TRISC4
CREN
SYNC
Bit 4
INTE
TXIE
TXIF
TRISC3
ADDEN
RABIE
SSPIE
SSPIF
Bit 3
—
TMR0IF
CCP1IE
CCP1IF
TRISC2
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
16.3.2.2
1.
2.
3.
4.
5.
6.
7.
8.
BRGH
FERR
Bit 2
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the CREN and SREN bits.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
Verify address detection is disabled by clearing
the ADDEN bit of the RCSTA register.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
INTF
Bit 1
transmission
Synchronous Slave Transmission
Setup
TMR1IE
TMR1IF
TRISC0
RABIF
RX9D
TX9D
Bit 0
2010 Microchip Technology Inc.
by
0000 000x
0000 0000
0000 0000
0000 000x
1111 1111
0000 0000
0000 -010
POR, BOR
Value on
writing
the
0000 000x
0000 0000
0000 0000
0000 000x
1111 1111
0000 0000
0000 -010
Value on
all other
Resets
Least
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