MSC8144SVT1000A Freescale Semiconductor, MSC8144SVT1000A Datasheet - Page 64
MSC8144SVT1000A
Manufacturer Part Number
MSC8144SVT1000A
Description
IC DSP QUAD 1GHZ 783FCPBGA
Manufacturer
Freescale Semiconductor
Series
MSC81xx StarCorer
Type
SC3400 Corer
Datasheet
1.MSC8144VT800A.pdf
(80 pages)
Specifications of MSC8144SVT1000A
Interface
Ethernet, I²C, SPI, TDM, UART, UTOPIA
Clock Rate
1.0GHz
Non-volatile Memory
External
On-chip Ram
10.5MB
Voltage - I/o
3.30V
Voltage - Core
1.00V
Operating Temperature
0°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MSC8144SVT1000A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 40
Figure 41
3
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
3.1
3.1.1
Use the following guidelines for power-on sequencing:
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4 V/ns.
64
•
•
•
There are no dependencies in power-on/power-off sequence between V
There are no dependencies in power-on/power-off sequence between RapidIO supplies: V
V
V
shows the test access port timing diagram
DDRIOPLL
DDPLL
shows the TRST timing diagram.
(Input)
Hardware Design Considerations
TRST
Start-up Sequencing Recommendations
Power-on Sequence
(Output)
(Output)
(Input)
(Input)
should be coupled with the V
TMS
TDO
TDO
TCK
TDI
and other MSC8144 supplies.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
t
TRST
Figure 40. Test Access Port Timing
t
TDOHOZ
t
TDOHOV
DD
Figure 41. TRST Timing
power rail with extremely low impedance path.
t
Output Data Valid
TDIVKH
Input Data Valid
DDM3
and V
t
TDIXKH
DD
supplies.
DDSXC
Freescale Semiconductor
, V
DDSXP
,