ISL12020MIRZ-T7A Intersil, ISL12020MIRZ-T7A Datasheet - Page 16

• Manufacturer Part Number: ISL12020MIRZ-T7A
• Description: IC RTC/CALENDAR TEMP SNSR 20DFN
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12020MIRZ-T7A

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a
valid read of the respective status register (with a valid
STOP condition). When the ARST is cleared to “0”, the
user must manually reset the ALM, LVDD, LBAT85, and
LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this
bit is “0”. Upon initialization or power-up, the WRTC must
be set to “1” to enable the RTC. Upon the completion of a
valid write (STOP), the RTC starts counting. The RTC
internal 1Hz signal is synchronized to the STOP condition
during a valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will
operate in the interrupt mode, where an active low pulse
width of 250ms will appear at the IRQ/F
the RTC is triggered by the alarm, as defined by the
alarm registers (0Ch to 11h). When the IM bit is cleared
to “0”, the alarm will operate in standard mode, where
the IRQ/F
is cleared to “0”.
FREQUENCY OUTPUT AND INTERRUPT BIT
(FOBATB)
This bit enables/disables the IRQ/F
battery-backup mode (i.e. V
When the FOBATB is set to “1”, the IRQ/F
disabled during battery-backup mode. This means that
both the frequency output and alarm output functions
are disabled. When the FOBATB is cleared to “0”, the
IRQ/F
Note that the open drain IRQ/F
pull-up to the battery voltage to operate in
battery-backup mode.
FREQUENCY OUT CONTROL BITS (FO<3:0>)
These bits enable/disable the frequency output function
and select the output frequency at the IRQ/F
See Table 5 for frequency selection. Default for the
ADDR
08h
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
IM BIT
OUT
0
1
ARST WRTC
OUT
7
pin is enabled during battery-backup mode.
pin will be set low until the ALM status bit
6
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By
Alarm
INTERRUPT/ALARM FREQUENCY
IM
TABLE 4.
5
16
BAT
FOBATB FO3 FO2 FO1 FO0
OUT
4
power source active).
OUT
pin will need a
3
pin during
OUT
OUT
2
pin when
OUT
pin is
1
ISL12020M
pin.
0
ISL12020M is FO<3:0> = 1h, or 32.768kHz output
(F
will override the alarm mode at the IRQ/F
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
This bit clears Time Stamp V
Time Stamp Battery to V
default setting is 0 (CLRTS = 0) and the Enabled setting
is 1 (CLRTS = 1).
V
These bits set the trip level for the V
that V
the LVDD bit in the Status Register is set to “1”. See
Table 6.
09h
FREQUENCY,
ADDR
TABLE 5. FREQUENCY SELECTION OF IRQ/F
DD
OUT
V
DD
32768
F
4096
1024
1/16
1/32
Brownout Trip Voltage BITS (V
1/2
1/4
1/8
OUT
64
32
16
DD
0
8
4
2
1
Trip2
0
0
0
0
1
1
is ON). When the frequency mode is enabled, it
CLRTS
has dropped below a preset level. In this event,
7
TABLE 6. V
6
UNIT
0
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
V
S
DD
5
0
Trip1
0
0
1
1
0
0
4
0
FO3
DD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DD
3
0
Registers (TSB2V). The
DD
TRIP LEVELS
V
V
DD
DD
to Battery (TSV2B) and
2
Trip2
FO2
Trip0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DD
V
alarm, indicating
DD
DD
FO1
OUT
1
Trip1
February 11, 2010
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Trip<2:0>)
VOLTAGE
OUT
pin.
2.295
2.550
2.805
3.060
4.250
4.675
TRIP
(V)
V
DD
FN6667.4
FO0
PIN
0
Trip0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1