ISL12022IBZ-T7A Intersil, ISL12022IBZ-T7A Datasheet - Page 23

• Manufacturer Part Number: ISL12022IBZ-T7A
• Description: IC RTC/CALENDAR TEMP SNSR 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12022IBZ-T7A

• Memory Size: 128B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The practical range of Actual AlphaH values is from
-0.020 to -0.060.
The ALPHAH register should only be changed while the TSE
(Temp Sense Enable) bit is “0”.
User Registers (Accessed by Using Slave
Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
I
The ISL12022 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12022 operates as a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
2
C Serial Interface
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
2
23
C interface is conducted by
START
FIGURE 14. VALID DATA CHANGES, START AND STOP CONDITIONS
START
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
1
STABLE
DATA
ISL12022
CHANGE
DATA
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 14). On power-up of the ISL12022, the SDA pin is in
the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12022 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 14). A START condition is ignored during the
power-up sequence.
All I
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 14). A STOP condition at the end
of a read operation or at the end of a write operation to
memory only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the 8 bits of data (see Figure 15).
2
2
C interface operations must begin with a START
C interface operations must be terminated by a STOP
STABLE
DATA
8
HIGH IMPEDANCE
STOP
ACK
9
June 23, 2009
FN6659.2