LFEC10E-3F484C Lattice, LFEC10E-3F484C Datasheet - Page 15

• Manufacturer Part Number: LFEC10E-3F484C
• Description: FPGA - Field Programmable Gate Array 10.2K LUTs
• Manufacturer: Lattice

Specifications of LFEC10E-3F484C

• Number Of Logic Blocks: 1280
• Number Of Macrocells: 10200
• Number Of Programmable I/os: 288
• Data Ram Size: 282624
• Delay Time: 3 ns
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 10.2 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-14. DCS Waveforms
sysMEM Memory
The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-
Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
SEL
CLK0
DCSOUT
CLK1
Single Port
True Dual Port
Pseudo Dual Port
Memory Mode
2-12
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
256 x 36
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
512 x 18
LatticeECP/EC Family Data Sheet
Architecture