LFX125EB-04FN256C Lattice, LFX125EB-04FN256C Datasheet - Page 20
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LFX125EB-04FN256C
Manufacturer Part Number
LFX125EB-04FN256C
Description
FPGA - Field Programmable Gate Array E-Ser139K Gt ispJTAG 2.5/3.3V -4 Spd
Manufacturer
Lattice
Specifications of LFX125EB-04FN256C
Number Of Macrocells
1936
Number Of Programmable I/os
160
Data Ram Size
94208
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.65 V
Number Of Gates
139 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFX125EB-04FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-
lar I/O interfaces requires an additional V
Typically an output will be terminated to V
The third type of interface standards are the differential standards LVDS, BLVDS, and LVPECL. The differential
standards require two I/O pins to create the differential pair. The logic level is determined by the difference in the
two signals. Table 6 lists how these interface standards are implemented in the ispXPGA devices.
For more information on sysIO capability, refer to TN1000,
Figure 19. sysIO Banks per Device
Table 4. Number of I/Os per Bank
V
V
V
V
CCO0
GND
CCO1
GND
REF0
REF1
XPGA 1200
XPGA 500
XPGA 200
XPGA 125
I/O N
I/O N
I/O 0
I/O 0
Device
REF
TT
Bank 7
Bank 2
at the receiving end of the transmission line it is driving.
signal. At the system level a termination voltage, V
Max. Number of I/Os per Bank (N)
16
sysIO Usage Guidelines for Lattice
Bank 6
Bank 3
62
42
26
22
ispXPGA Family Data Sheet
I/O N
I/O N
I/O 0
I/O 0
V
V
GND
V
V
GND
CCO5
REF5
CCO4
REF4
Devices.
TT
, is also required.
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