A42MX16-PLG84 Actel, A42MX16-PLG84 Datasheet - Page 66
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A42MX16-PLG84
Manufacturer Part Number
A42MX16-PLG84
Description
FPGA - Field Programmable Gate Array 24K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A42MX16-PLG84
Processor Series
A42MX16
Core
IP Core
Number Of Macrocells
608
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
140
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
24 K
Package / Case
PLCC-84
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A42MX16-PLG84A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A42MX16-PLG84I
Manufacturer:
ACTEL
Quantity:
101
Company:
Part Number:
A42MX16-PLG84I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 35 •
1 -6 0
Parameter Description
Input Module Propagation Delays
t
t
t
t
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
t
t
f
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
INYH
INYL
INGH
INGL
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
HEXT
P
MAX
40MX and 42MX FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Pad-to-Y HIGH
Pad-to-Y LOW
G to Y HIGH
G to Y LOW
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Input Latch External
Set-Up
Input Latch External
Hold
Minimum Period
Maximum Frequency FO = 32
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 32
FO = 384
FO = 384
2
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
5.7
6.6
5.3
6.2
0.0
0.0
3.9
4.5
7.0
7.7
CCA
142
129
1.5
1.1
2.0
2.0
2.6
2.9
3.3
3.6
5.1
4.4
4.8
5.3
6.2
0.5
2.2
= 3.0V, T
v6.1
‘–2’ Speed
6.3
7.4
5.9
6.9
0.0
0.0
4.3
4.9
7.8
8.6
J
= 70°C)
129
117
1.6
1.3
2.2
2.2
2.9
3.2
3.6
4.0
5.6
4.8
5.3
5.9
6.9
0.5
2.4
‘–1’ Speed
7.1
8.3
6.7
7.9
0.0
0.0
4.9
5.6
8.4
9.3
119
108
1.9
1.4
2.5
2.5
3.2
3.7
4.1
4.6
6.4
5.5
6.0
6.7
7.9
0.6
2.7
‘Std’ Speed
10.7
8.4
9.8
7.8
9.2
0.0
0.0
5.7
6.6
9.7
103
2.2
1.7
2.9
2.9
3.8
4.3
4.9
5.4
7.5
6.5
7.1
7.8
9.2
0.7
3.2
94
11.8
13.7
11.0
12.9
16.2
17.8
‘–F’ Speed
0.0
0.0
8.0
9.2
10.5
11.0
12.9
3.1
2.4
4.1
4.1
5.3
6.1
6.8
7.6
9.0
9.9
1.0
4.5
62
56
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns