A3PE1500-PQG208 Actel, A3PE1500-PQG208 Datasheet - Page 59

• Manufacturer Part Number: A3PE1500-PQG208
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-PQG208

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 147
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-72 • Minimum and Maximum DC Input and Output Levels
Figure 2-19 • AC Loading
Table 2-73 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-74 • SSTL3 Class I
SSTL3 Class I
Drive
Strength
14 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.2
*
Speed
Grade
Std.
–1
–2
Note:
Measuring point = V
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Worst-Case VCCI = 3.0 V, VREF = 1.5 V
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
t
DOUT
0.66
0.56
0.49
Min.
–0.3 VREF – 0.2 VREF + 0.2
V
Input High (V)
trip
VREF + 0.2
VIL
. See
2.31
1.96
1.72
t
DP
Max.
V
Table 2-15 on page 2-19
0.04
0.04
0.03
t
DIN
Min.
V
Test Point
1.25
1.06
0.93
Measuring
t
Point* (V)
PY
VIH
J
1.5
= 70°C, Worst-Case VCC = 1.425 V,
Max.
3.6
V
t
0.43
0.36
0.32
EOUT
SSTL3
Class I
for a complete table of trip points.
25
R e v i s i o n 9
Max.
VOL
0.7
V
VREF (typ.) (V)
2.35
2.00
1.75
t
ZL
V
TT
VCCI – 1.1 14 14
1.5
50
30 pF
VOH
Min.
1.84
1.56
1.37
t
V
ZH
Table 2-6 on page 2-5
mA mA
t
I
LZ
OL
VTT (typ.) (V)
I
OH
1.485
t
HZ
ProASIC3E Flash Family FPGAs
Max.
I
mA
OSL
54
4.59
3.90
3.42
t
ZLS
1
for derating values.
t
4.07
3.46
3.04
Max.
I
mA
ZHS
OSH
C
51
LOAD
1
30
µA
(pF)
10 10
I
Units
IL
ns
ns
ns
2
µA
2- 47
I
IH
2