A42MX16-PQG160 Actel, A42MX16-PQG160 Datasheet - Page 9

• Manufacturer Part Number: A42MX16-PQG160
• Description: FPGA - Field Programmable Gate Array 24K System Gates
• Manufacturer: Actel

Specifications of A42MX16-PQG160

• Processor Series: A42MX16
• Core: IP Core
• Number Of Macrocells: 608
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 140
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 24 K
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A42MX24 and A42MX36 devices contain D-modules,
which are arranged around the periphery of the device.
D-modules contain wide-decode circuitry, providing a
fast, wide-input AND function similar to that found in
CPLD architectures
A42MX24 and A42MX36 devices to perform wide-
decode functions at speeds comparable to CPLDs and
PALs. The output of the D-module has a programmable
inverter for active HIGH or LOW assertion. The D-module
output is hardwired to an output pin, and can also be
fed back into the array to be incorporated into other
logic.
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules
that
asynchronous applications. The SRAM modules are
arranged in 256-bit blocks that can be configured as 32x8
or 64x4. SRAM modules can be cascaded together to
form memory spaces of user-definable width and depth.
A block diagram of the A42MX36 dual-port SRAM block
is shown in
The A42MX36 SRAM modules are true dual-port
structures containing independent read and write ports.
Each SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
Figure 1-5 • A42MX36 Dual-Port SRAM Block
have
Figure
been
1-5.
WRAD[5:0]
(Figure
BLKEN
optimized
MODE
WCLK
WEN
1-4). The D-module allows
Latches
Logic
Write
for
WD[7:0]
synchronous
[5:0]
Write
Logic
Port
Latches
32 x 8 or 64 x 4
SRAM Module
Routing Tracks
(256 Bits)
or
v6.1
[7:0]
RD[7:0]
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]), and eight outputs (RD[7:0]), which are
connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
FIFO and LIFO queues. The ACTgen Macro Builder within
Actel's Designer software provides capability to quickly
design memory functions with the SRAM blocks. Unused
SRAM blocks can be used to implement registers for
other user logic within the design.
Figure 1-4 • A42MX24 and A42MX36 D-Module
Implementation
Read
Logic
Port
Programmable
Inverter
7 Inputs
[5:0]
Latches
Feedback to Array
Read
Logic
40MX and 42MX FPGA Families
RDAD[5:0]
REN
RCLK
Hard-Wire to I/O
1-3