LFXP10C-3FN256I Lattice, LFXP10C-3FN256I Datasheet - Page 326
LFXP10C-3FN256I
Manufacturer Part Number
LFXP10C-3FN256I
Description
FPGA - Field Programmable Gate Array 9.7K LUTs 188 IO 1.8 /2.5/3.3V -3 Spd I
Manufacturer
Lattice
Specifications of LFXP10C-3FN256I
Number Of Programmable I/os
188
Data Ram Size
221184
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LFXP10C-3FN256I
Manufacturer:
LATTICE
Quantity:
201
Company:
Part Number:
LFXP10C-3FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice ispTRACY Usage Guide
Figure 14-10. ispLA Project Setup Window - Event Pattern Setup
The Event Pattern window configures the patterns for EV0 and EV1. Pattern 0 corresponds to EV0 and Pattern 1
corresponds to EV1. The sample types for trigger signals depends on whether the signal is edge or level sensitive.
If the signal is level sensitive, in the middle pattern window, only logic 0 (0) ,logic (1) or don't care (X) are available.
For edge sensitive signals, the options are logic 0 (0), logic 1 (1), rising (R), falling (F), both/either edge (B) or don't
care (X). In this window, changes to the pattern are made in the center section (Pattern 1 or Pattern 0) and the
changes are reflected in the right section.
To begin sampling , click on the green run button. Sampling will complete when the trigger conditions are met. The
data will be uploaded through the JTAG cable and results displayed I the Signal Analysis window. Figure 14-11
shows the Signal Analysis window after a data capture cycle.
Figure 14-11. ispLA Signal Analysis Window
14-8
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