AGL400V2-FGG144 Actel, AGL400V2-FGG144 Datasheet - Page 47

• Manufacturer Part Number: AGL400V2-FGG144
• Description: FPGA - Field Programmable Gate Array 400K System Gates
• Manufacturer: Actel

Specifications of AGL400V2-FGG144

• Processor Series: AGL400
• Core: IP Core
• Number Of Logic Blocks: 12
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 97
• Data Ram Size: 54 Kbit
• Supply Voltage (max): 1.5 V
• Supply Current: 27 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 400 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
3.3 V
LVTTL /
3.3 V
LVCMOS
3.3 V
LVCMOS
Wide
Range
2.5 V
LVCMOS
1.8 V
LVCMOS
1.5 V
LVCMOS
1.2 V
LVCMOS
1.2 V
LVCMOS
Wide
Range
3.3 V PCI
3.3 V
PCI-X
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
5. For specific junction temperature and voltage supply levels, refer to
equivalent software default drive strength. These values are for normal ranges only.
for connectivity. This resistor is not required during normal operation.
2
3
100 µA
100 µA
12 mA
12 mA
PCI-X
2 mA
spec
spec
8 mA
4 mA
PCI
Commercial-Case Conditions: T
standard)
Applicable to Standard Plus I/O Banks
Per
Per
12
12
12
2
2
8
4
–
–
High
High
High
High
High
High
High
High
High
10
10 25
5
5
5
5
5
5
5
25
–
–
–
–
–
–
–
2
2
1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns
1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns
1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns
1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns
1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns
1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns
1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns
1.55 2.53 0.26 0.84 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns
1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns
J
= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
R ev i si o n 1 8
μ
A drive strength only. The configuration will not operate at the
Table 2-6 on page 2-7
IGLOO Low Power Flash FPGAs
for derating values.
Figure 2-12 on page 2-79
2- 33