AGLN125V2-ZVQG100 Actel, AGLN125V2-ZVQG100 Datasheet - Page 83
![FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano](/photos/16/14/161495/tqfp-100_sml.jpg)
AGLN125V2-ZVQG100
Manufacturer Part Number
AGLN125V2-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN125V2-ZVQG100
Processor Series
AGLN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Supply Voltage (max)
1.5 V
Supply Current
18 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.2 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AGLN125V2-ZVQG100
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
AGLN125V2-ZVQG100I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-99 • AGLN125 Global Resource
Table 2-100 • AGLN250 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
J
J
= 70°C, VCC = 1.14 V
= 70°C, VCC = 1.14 V
R ev i si o n 1 1
Table 2-7 on page 2-7
Table 2-7 on page 2-7
IGLOO nano Low Power Flash FPGAs
for derating values.
for derating values.
Min.
Min.
2.08
2.15
2.11
2.19
1
1
Std.
Std.
Max.
Max.
2.54
2.77
0.62
2.57
2.81
0.62
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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