A3P400-FGG484 Actel, A3P400-FGG484 Datasheet - Page 103
A3P400-FGG484
Manufacturer Part Number
A3P400-FGG484
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-FGG484
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-109 • A3P060 Global Resource
Table 2-110 • A3P125 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Commercial-Case Conditions: T
Commercial-Case Conditions: T
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Description
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.425 V
R e v i s i o n 9
Min.
Min.
Table 2-6 on page 2-6
Table 2-6 on page 2-6
0.71
0.70
0.77
0.76
1
1
–2
–2
Max.
Max.
0.93
0.96
0.26
0.99
1.02
0.26
2
2
Min.
Min.
0.81
0.80
0.87
0.87
1
1
–1
–1
Max.
for derating values.
Max.
for derating values.
1.05
1.09
0.29
1.12
1.16
0.29
ProASIC3 Flash Family FPGAs
2
2
Min.
Min.
0.95
0.94
1.03
1.02
Std.
1
Std.
1
Max.
Max.
1.24
1.28
0.34
1.32
1.37
0.34
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 89
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