APA300-PQG208 Actel, APA300-PQG208 Datasheet - Page 148

• Manufacturer Part Number: APA300-PQG208
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-PQG208

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3 -6 4
Number
ProASIC
R10
P21
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
Pin
P22
P23
P24
P25
P26
P27
P28
P29
P30
R1
R2
R3
R4
R5
R6
R7
R8
R9
PLUS
896-Pin FBGA
I/O / GLMX1
Function
APA750
I/O / GL1
NPECL1
Flash Family FPGAs
AGND
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
I/O / GLMX1
APA1000
Function
I/O / GL1
NPECL1
AGND
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
Number
R29
T10
R25
R26
R27
R28
R30
Pin
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T1
T2
T3
T4
T5
T6
T7
T8
T9
PPECL1 / Input PPECL1 / Input
PPECL2 / Input PPECL2 / Input
896-Pin FBGA
I/O / GLMX2
Function
APA750
I/O / GL2
I/O / GL4
I/O / GL3
NPECL2
AGND
AVDD
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
v5.9
DDP
DDP
DD
DD
I/O / GLMX2
APA1000
Function
I/O / GL2
I/O / GL4
I/O / GL3
NPECL2
AGND
AVDD
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DD
DD
Number
U10
U22
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U23
U24
U25
U26
U27
U28
U29
U30
Pin
T29
T30
U9
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
896-Pin FBGA
Function
APA750
AVDD
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DD
DD
APA1000
Function
AVDD
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DD
DD