LFE2M35E-6FN484C Lattice, LFE2M35E-6FN484C Datasheet - Page 92

• Manufacturer Part Number: LFE2M35E-6FN484C
• Description: FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -6 Spd
• Manufacturer: Lattice
• Series: LatticeECP2Mr

Specifications of LFE2M35E-6FN484C

• Number Of Macrocells: 34000
• Maximum Operating Frequency: 357 MHz
• Number Of Programmable I/os: 303
• Data Ram Size: 2151424
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 34000
• No. Of Macrocells: 16000
• No. Of Speed Grades: 6
• Total Ram Bits: 2101Kbit
• No. Of I/o's: 303
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-12. Transmitter and Receiver Block Diagram
HDOUTPi
HDOUTNi
HDINPi
HDINNi
Transmitter
Receiver
REFCLK
EQ
TX PLL
SERDES
REFCLK
CDR
Serializer
8:1/10:1
Transmit Clock
T4
Deserializer
R1
1:8/1:10
SERDES Bridge
R2
BYPASS
Polarity
Adjust
BYPASS
Polarity
Adjust
T3
Recovered Clock
3-40
BYPASS
R3
WA
Encoder
BYPASS
BYPASS
DEC
PCS
T2
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
R4
BYPASS
Elastic
Buffer
FIFO
R5
FPGA Bridge
Sample
Down
FIFO
Sample
R6
FIFO
Up
BYPASS
T1
FPGA Core
FPGA
EBRD Clock
Receive Data
FPGA
Receive Clock
Transmit Data
FPGA
Transmit Clock