LCMXO640C-5TN144C Lattice, LCMXO640C-5TN144C Datasheet - Page 19

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LCMXO640C-5TN144C

Manufacturer Part Number
LCMXO640C-5TN144C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 113 I/O
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640C-5TN144C

Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
4.9 ns
Number Of Programmable I/os
256
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO640C-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LCMXO640C-5TN144C-4I
Quantity:
1 146
Lattice Semiconductor
2. Left and Right sysIO Buffer Pairs
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all V
Banks that are critical to the application. For more information on controlling the output logic state with valid input
logic levels during power-up in MachXO devices, see details of additional technical documentation at the end of
this data sheet.
The V
ers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers
should be powered up along with the FPGA core fabric. Therefore, V
together with the V
Supported Standards
The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL
output emulation is supported on all devices. The MachXO1200 and MachXO2280 support on-chip LVDS output
buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and
LVPECL are supported on all Banks of MachXO1200 and MachXO2280 devices. PCI support is provided in the top
Banks of the MachXO1200 and MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices
in the MachXO family.
Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the
MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see
the details of additional technical documentation at the end of this data sheet.
Table 2-8. I/O Support Device by Device
Number of I/O Banks
Type of Input Buffers
Types of Output Buffers
Differential Output
Emulation Capability
PCI Support
The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a
differential driver per output pair. The referenced input buffer can also be configured as a differential input
buffer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is asso-
ciated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the
negative side of the differential I/O.
CC
CCIO
and V
Banks are active with valid input logic levels to properly control the output logic states of all the I/O
CCAUX
CC
supply the power to the FPGA core fabric, whereas the V
and V
2
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
CCAUX
MachXO256
supplies
4
Single-ended
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
All I/O Banks
No
MachXO640
2-16
CC
and V
CCIO
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
supplies should be powered up before or
MachXO1200
CCAUX
CCIO
MachXO Family Data Sheet
have reached satisfactory levels.
supplies power to the I/O buff-
8
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
Differential buffers with
true LVDS outputs (50%
on left and right side)
All I/O Banks
Top side only
MachXO2280
Architecture

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