ispLSI 1016E-80LJN Lattice, ispLSI 1016E-80LJN Datasheet - Page 11
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ispLSI 1016E-80LJN
Manufacturer Part Number
ispLSI 1016E-80LJN
Description
CPLD - Complex Programmable Logic Devices USE ispMACH 4000V
Manufacturer
Lattice
Datasheet
1.ISPLSI_1016E-80LJN.pdf
(17 pages)
Specifications of ispLSI 1016E-80LJN
Number Of Macrocells
64
Maximum Operating Frequency
100 MHz
Delay Time
18.5 ns
Number Of Programmable I/os
32
Operating Supply Voltage
5 V
Supply Current
90 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-44
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Outputs
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
oen
odis
gy0
gy1/2
gcp
ioy1/2
iocp
gr
47
48
49
50
51
52
53
54
55
#
2
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
DESCRIPTION
1
10
Specifications ispLSI 1016
MIN. MAX.
4.5
3.5
1.0
3.5
1.0
–
–
–
–
-80
3.0
5.0
5.0
4.5
5.5
5.0
5.5
5.0
9.0
MIN. MAX.
6.0
4.6
1.3
4.6
1.3
–
–
–
–
-60
12.0
4.0
6.7
6.7
6.0
7.3
6.6
7.3
6.6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns