LCMXO640C-4TN144C Lattice, LCMXO640C-4TN144C Datasheet - Page 17

• Manufacturer Part Number: LCMXO640C-4TN144C
• Description: CPLD - Complex Programmable Logic Devices 640 LUTS 113 I/O
• Manufacturer: Lattice

Specifications of LCMXO640C-4TN144C

• Memory Type: SRAM
• Number Of Macrocells: 320
• Maximum Operating Frequency: 550 MHz
• Delay Time: 4.2 ns
• Number Of Programmable I/os: 144
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 17 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Programmable Type: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-15. Group of Six Programmable I/O Cells
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-16
shows the MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Six PIOs
This structure is used on the top
and bottom of MachXO devices
2-14
PIO A
PIO B
PIO C
PIO D
PIO E
PIO F
PADB "C"
PADA "T"
PADC "T"
PADE "T"
PADF "C"
PADD "C"
MachXO Family Data Sheet
Architecture