LCMXO640C-3TN144C Lattice, LCMXO640C-3TN144C Datasheet - Page 6
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LCMXO640C-3TN144C
Manufacturer Part Number
LCMXO640C-3TN144C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 113 I/O
Manufacturer
Lattice
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO640C-3TN144C
Memory Type
SRAM
Number Of Macrocells
320
Delay Time
4.9 ns
Number Of Programmable I/os
113
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
FPBGA-256-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3TN144C
Manufacturer:
BEILING
Quantity:
15 000
Company:
Part Number:
LCMXO640C-3TN144C
Manufacturer:
Lattice
Quantity:
581
Company:
Part Number:
LCMXO640C-3TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO640C-3TN144C
Manufacturer:
LATTICE/莱迪斯
Quantity:
20 000
Lattice Semiconductor
Figure 2-3. Top View of the MachXO256 Device
PFU Blocks
The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will
use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs
and 25 outputs associated with each PFU block.
Figure 2-4. PFU Diagram
Slice
Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice.
The registers in the Slice can be configured for positive/negative and edge/level clocks.
FCIN
Latch
FF/
LUT4 &
CARRY
D
Programmable
Function
Units with
RAM (PFUs)
Slice 0
JTAG Port
Latch
FF/
CARRY
LUT4 &
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
CARRY
LUT4 &
D
Routing
Routing
2-3
From
To
Latch
FF/
CARRY
LUT4 &
D
Slice 2
Programmable Function
Units without RAM (PFFs)
PIOs Arranged
into sysIO Banks
Latch
FF/
CARRY
LUT4 &
D
MachXO Family Data Sheet
Latch
FF/
CARRY
LUT4 &
D
Slice 3
Latch
FF/
CARRY
LUT4 &
D
FCO
Architecture