LC4064V-5TN48C Lattice, LC4064V-5TN48C Datasheet - Page 43

• Manufacturer Part Number: LC4064V-5TN48C
• Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
• Manufacturer: Lattice

Specifications of LC4064V-5TN48C

• Memory Type: EEPROM
• Number Of Macrocells: 64
• Number Of Product Terms Per Macro: 80
• Maximum Operating Frequency: 400 MHz
• Delay Time: 2.5 ns
• Number Of Programmable I/os: 352
• Operating Supply Voltage: 3.3 V
• Supply Current: 12 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-48
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Package: 48TQFP
• Family Name: ispMACH® 4000V
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 5 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 36
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 90 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispMACH 4000V/B/C/Z Power Supply and NC Connections
VCC
VCCO0
VCCO (Bank 0)
VCCO1
VCCO (Bank 1)
GND
GND (Bank 0)
GND (Bank 1)
NC
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
the bank shown.
ascending horizontally.
Signal
11, 33
6
28
12, 34
5
27
—
44-pin TQFP
2
12, 36
6
30
13, 37
5
29
—
48-pin TQFP
2
K2, A9
F3
E8
H3, C8
D3
G8
4032Z: A8, B10, E1,
E3, F8, F10, J1, K3
43
56-ball csBGA
ispMACH 4000V/B/C/Z Family Data Sheet
3
25, 40, 75, 90
13, 33, 95
45, 63, 83
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
100-pin TQFP
1
2
32, 51, 96, 115
3, 17, 30, 41, 122
58, 67, 81, 94, 105
1, 33, 65, 97
10, 24, 40, 113, 123
49, 59, 74, 88, 104
—
128-pin TQFP
2