LC4256ZE-7TN100I Lattice, LC4256ZE-7TN100I Datasheet - Page 24
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LC4256ZE-7TN100I
Manufacturer Part Number
LC4256ZE-7TN100I
Description
CPLD - Complex Programmable Logic Devices 64 I/O ULT LW PWR 256MC 1.8V 7.5NS IND
Manufacturer
Lattice
Series
ispMACH®r
Datasheet
1.LC4064ZE-5TN100C.pdf
(60 pages)
Specifications of LC4256ZE-7TN100I
Memory Type
EEPROM
Number Of Macrocells
256
Maximum Operating Frequency
178.57 MHz
Delay Time
7.5 ns
Number Of Programmable I/os
64
Operating Supply Voltage
1.8 V
Supply Current
0.341 mA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
1.9 V
Supply Voltage (min)
1.7 V
Programmable Type
CPLD
Voltage - Input
1.7 V ~ 1.9 V
Speed
7.5ns
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4256ZE-7TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
ispMACH 4000ZE Internal Timing Parameters
Lattice Semiconductor
In/Out Delays
t
t
t
t
t
t
t
t
t
t
Routing Delays
t
t
t
t
t
t
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IN
GCLK_IN
GOE
BUF
EN
DIS
PGSU
PGH
PGPW
PGRT
ROUTE
PDi
MCELL
INREG
FBK
ORP
S
S_PT
H
ST
ST_PT
HT
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
PDLi
SRi
Parameter
Input Buffer Delay
Global Clock Input Buffer Delay
Global OE Pin Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
Input Power Guard Setup Time
Input Power Guard Hold Time
Input Power Guard BIE Minimum Pulse Width
Input Power Guard Recovery Time Following BIE
Dissertation
Delay through GRP
Macrocell Propagation Delay
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
Output Routing Pool Delay
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
D-Register Hold Time
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
T-Resister Hold Time
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
Propagation Delay through Transparent Latch to Output/
Feedback MUX
Asynchronous Reset or Set to Output/Feedback MUX
Delay
Over Recommended Operating Conditions
Description
24
ispMACH 4000ZE Family Data Sheet
Min.
0.70
1.25
1.50
0.90
1.45
1.50
0.85
1.45
1.15
0.90
1.00
0.00
0.70
1.45
1.40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LC4032ZE
-4
Max.
0.85
1.60
2.25
0.75
2.25
1.35
3.30
0.00
5.00
5.00
1.60
0.25
0.65
0.90
0.55
0.30
0.35
0.40
0.30
0.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0.85
1.85
1.65
1.05
1.65
1.65
0.80
1.45
1.30
1.10
2.00
0.00
0.95
1.85
1.80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LC4064ZE
-4
Max.
0.90
1.60
2.25
0.90
2.25
1.35
3.55
0.00
5.00
5.00
1.70
0.25
0.65
1.00
0.55
0.30
0.40
0.35
0.25
0.30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns