LCMXO640C-3TN100C Lattice, LCMXO640C-3TN100C Datasheet - Page 45
![CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O](/photos/16/2/160258/tqfp-100_sml.jpg)
LCMXO640C-3TN100C
Manufacturer Part Number
LCMXO640C-3TN100C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 74 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO640C-3TN100C
Memory Type
SRAM
Number Of Macrocells
320
Delay Time
4.9 ns
Number Of Programmable I/os
74
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.9ns
Voltage Supply - Internal
1.71 V ~ 3.465 V
Number Of Logic Elements/blocks
-
Number Of Gates
-
Number Of I /o
74
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
STC
Quantity:
12 000
Company:
Part Number:
LCMXO640C-3TN100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO640C-3TN100C
Manufacturer:
LATTICE
Quantity:
20 000
www.latticesemi.com
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
December 2006
Signal Descriptions
General Purpose
P[Edge] [Row/Column
Number]_[A/B/C/D/E/F]
GSRN
TSALL
NC
GND
V
V
V
SLEEPN
PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins)
[LOC][0]_PLL[T, C]_IN
[LOC][0]_PLL[T, C]_FB
PCLK [n]_[1:0]
Test and Programming (Dedicated pins)
TMS
TCK
TDI
TDO
1. Applies to MachXO “C” devices only. NC for “E” devices.
CC
CCAUX
CCIOx
Signal Name
1
I/O
I/O
—
—
—
—
—
—
—
—
O
I
I
I
I
I
I
[Edge] indicates the edge of the device on which the pad is located. Valid edge designa-
tions are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the
PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.
When Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected.
Some of these user programmable pins are shared with special function pins. When not
used as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the
I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or
those not bonded to a package pin). The default during configuration is for user-program-
mable I/Os to be tri-stated with an internal pull-up resistor enabled.
Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O
pin.
TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the
outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin.
No connect.
GND - Ground. Dedicated pins.
VCC - The power supply pins for core logic. Dedicated pins.
VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits
including all the differential and referenced input buffers. Dedicated pins.
V
Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates nor-
mally. This pin has a weak internal pull-up, but when unused, an external pull-up to V
recommended. When driven low, the device moves into Sleep mode after a specified time.
Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
Primary Clock Pads, n per side.
Test Mode Select input pin, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data input pin, used to load data into the device using an 1149.1 state machine.
Output pin -Test Data output pin used to shift data out of the device using 1149.1.
CCIO
- The power supply pins for I/O Bank x. Dedicated pins.
4-1
MachXO Family Data Sheet
Descriptions
Pinout Information
Pinouts_01.5
Data Sheet
CC
is