S29GL512P11TFI020 Spansion Inc., S29GL512P11TFI020 Datasheet - Page 58

Flash 3V 512Mb Mirrorbit lowest address100ns

S29GL512P11TFI020

Manufacturer Part Number
S29GL512P11TFI020
Description
Flash 3V 512Mb Mirrorbit lowest address100ns
Manufacturer
Spansion Inc.
Datasheet

Specifications of S29GL512P11TFI020

Memory Type
NOR
Memory Size
512 Mbit
Access Time
110 ns
Data Bus Width
8 bit, 16 bit
Architecture
Uniform
Interface Type
Page-mode
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
50 mA
Mounting Style
SMD/SMT
Operating Temperature
+ 85 C
Package / Case
TSOP-56
Memory Configuration
128K X 16
Ic Interface Type
Parallel
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
TSOP
No. Of Pins
56
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S29GL512P11TFI020
Manufacturer:
TDK
Quantity:
400 000
Part Number:
S29GL512P11TFI020
Manufacturer:
SPANSION20
Quantity:
600
58
JEDEC
11.7.2
Parameter
t
t
Std.
Ready
Ready
t
t
t
RPD
t
RP
RH
RB
Hardware Reset (RESET#)
Notes
1. V
2. V
3. If RESET# is not stable for t
4. V
The device does not permit any read and write operations.
A valid read operation returns FFh.
A hardware reset is required.
RESET# Pin Low (During Embedded Algorithms) to
Read Mode or Write mode
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode or Write mode
RESET# Pulse Width
Reset High Time Before Read
RESET# Low to Standby Mode
RY/BY# Recovery Time
IO
IO
CC
Parameter
< V
and V
maximum power-up current (RST=V
t
t
VIOS
t
VCS
RH
CC
CC
CE#, OE#
CE#, OE#
+ 200 mV.
RESET#
RESET#
RY/BY#
RY/BY#
ramp must be synchronized during power up.
Reset Low Time from rising edge of V
rising edge of RESET#
Reset Low Time from rising edge of V
rising edge of RESET#
Reset High Time before Read
VCS
Table 11.4 Hardware Reset (RESET#)
or t
Description
S29GL-P MirrorBit
VIOS
D a t a
:
Table 11.5 Power-up Sequence Timings
IL
Reset Timings NOT during Embedded Algorithms
) is 20 mA.
t
Ready
t
t
Reset Timings during Embedded Algorithms
RP
RP
Figure 11.7 Reset Timings
S h e e t
Description
t
Ready
®
Flash Family
CC
t
IO
RH
( P r e l i m i n a r y )
(or last Reset pulse) to
(or last Reset pulse) to
Min
Min
Min
Min
Min
Min
S29GL-P_00_A8 November 28, 2007
t
RB
Min
Min
Min
Speed
200
35
35
35
10
0
Speed
200
35
35
Unit
µs
µs
ns
Unit
µs
µs
µs
ns
µs
ns

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