GLS29SF040-55-4C-NHE Greenliant, GLS29SF040-55-4C-NHE Datasheet - Page 2

• Manufacturer Part Number: GLS29SF040-55-4C-NHE
• Description: Flash 512K X 8 55ns
• Manufacturer: Greenliant

Specifications of GLS29SF040-55-4C-NHE

• Data Bus Width: 8 bit
• Architecture: Sectored
• Timing Type: Asynchronous
• Interface Type: Parallel
• Access Time: 55 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 25 mA
• Mounting Style: SMD/SMT
• Organization: 512 KB x 8
• Memory Type: Flash
• Memory Size: 4 Mbit
• Operating Temperature: + 70 C
• Package / Case: PLCC-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
To meet high density, surface mount requirements, the
GLS29SF020/040 and GLS29VF020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
pin assignments are shown in Figures 2 and 3.
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the GLS29SF020/040 and
GLS29VF020/040 devices are controlled by CE# and
OE#, both have to be low for the system to obtain data
from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. Refer to the
Read cycle timing diagram in Figure 4 for further details.
Byte-Program Operation
The GLS29SF020/040 and GLS29VF020/040 devices
are programmed on a byte-by-byte basis. Before program-
ming, the sector where the byte exists must be fully erased.
The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software
Data Protection. The second step is to load byte address
and byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 16 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
©2010 Greenliant Systems, Ltd.
2 Mbit / 4 Mbit Small-Sector Flash
2
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The GLS29SF020/
040 and GLS29VF020/040 offer Sector-Erase mode. The
sector architecture is based on uniform sector size of 128
Bytes. The Sector-Erase operation is initiated by executing
a six-byte command sequence with Sector-Erase com-
mand (20H) and sector address (SA) in the last bus cycle.
The sector address is latched on the falling edge of the
sixth WE# pulse, while the command (20H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. For timing waveforms, see
Figure 9. Any commands issued during the Sector-Erase
operation are ignored.
Chip-Erase Operation
The GLS29SF020/040 and GLS29VF020/040 devices
provide a Chip-Erase operation, which allows the user to
erase the entire memory array to the “1s” state. This is use-
ful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the com-
mand sequence, Figure 10 for the timing diagram, and Fig-
ure 19 for the flowchart. Any commands written during the
Chip-Erase operation will be ignored.
Write Operation Status Detection
The GLS29SF020/040 and GLS29VF020/040 devices
provide two software means to detect the completion of a
Write (Program or Erase) cycle, in order to optimize the
system Write cycle time. The software detection includes
two status bits: Data# Polling (DQ
(DQ
the rising edge of WE# which initiates the internal Pro-
gram or Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
6
). The End-of-Write detection mode is enabled after
GLS29SF020 / GLS29SF040
GLS29VF020 / GLS29VF040
7
or DQ
7
) and Toggle Bit
S71160-15-000
6
. In order to pre-
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